POWRE: Nano-gate Engineering for Ultra-fast CMOS devices

POWRE：超快 CMOS 器件的纳米门工程

• 批准号: 0074800
• 负责人: Veena Misra
• 金额: $ 6.88万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-08-01 至 2002-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0074800&HistoricalAwards=false
• 关键词: POWRE; Nano; gate; Engineering; Ultra

0074800MisraTo obtain maximum performance from nanoscale CMOS devices, conventional polycrystalline silicon gate electrodes will have to be replaced by metallic layers. However, any replacement candidate for polysilicon must adhere to several criteria. Firstly, electrodes should not react with the underlying sub-1.0 nm gate dielectric. Secondly, the electrodes must be able to withstand high temperature processing in order to preserve the self-aligned structure of the MOS device, which has been the foundation of today's advanced technologies. Finally, to obtain desired threshold voltage for giga-scale performance, the electrodes must provide specific workfunctions, i.e. NMOS devices will require gates with workfunctions near 4 eV and PMOS devices will require gates with workfunctions near 5 eV. The need for two separate metals significantly complicates the process technology, both in material and cost issues.The goal of this POWRE project is to investigate alternate approaches for nano-gate electrode formation using workfunction modulation of conducting metal oxides. Transparent conducting oxides offer the flexibility of workfunction modulation via chemical composition changes. This property can be used to benefit nanoscale CMOS. The main theme behind this proposed activity is to deposit a single conducting oxide layer on both the NMOS and PMOS region dielectrics and then via non-critical masking steps, selectively implanting certain elements to modulate the workfunction on N and P regions. This would eliminate the need for two separate metal deposition steps and drastically simplify integration issues. Moreover, conducting metal oxides, never before considered for Si gate electrode applications, can also provide superior thermal and chemical stability. If the above proposed activities are feasible, i.e. workfunction of conducting metal oxides can be tuned in to match the CMOS requirements, then this work offers tremendous potential for nanoscale CMOS advancement.***

0074800misrato从纳米级CMOS设备中获得最大性能，常规的多晶硅栅极电极必须被金属层代替。 但是，任何替代候选人的多替代人都必须遵守几个标准。 首先，电极不应与基础下1.0 nm栅极介电反应。 其次，电极必须能够承受高温处理，以保留MOS设备的自对准结构，这一直是当今高级技术的基础。 最后，为了获得GIGA尺度性能的所需阈值电压，电极必须提供特定的工作函数，即NMOS设备将需要4 eV附近的工作函数的门，而PMOS设备将需要在5 ev附近的工作配置。 在材料和成本问题上，对两种单独的金属的需求显着使工艺技术变得复杂。该POWRE项目的目的是使用导电金属氧化物的工作函数调制调查纳米栅电极形成的替代方法。 透明导电氧化物通过化学成分变化提供了工作功能调制的灵活性。 该属性可用于使纳米级CMO受益。 这项提出的活动的主要主题是将单个导电氧化物层放在NMOS和PMOS区域介电上，然后通过非临界掩蔽步骤，选择性地植入某些元素以调节N和P区域的工作功能。 这将消除对两个单独的金属沉积步骤的需求，并极大地简化了集成问题。 此外，传导金属氧化物，从未考虑过用于Si Gate电极应用，也可以提供出色的热和化学稳定性。 如果以上提议的活动是可行的，即可以调节传导金属氧化物的工作功能以符合CMOS要求，那么这项工作为纳米级CMOS的进步提供了巨大的潜力。*** ***