Design techniques for three-dimensional integrated circuits challenges

应对三维集成电路挑战的设计技术

• 批准号: RGPIN-2017-04292
• 负责人: ElSankary, Kamal
• 金额: $ 1.75万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2020
• 资助国家: 加拿大
• 起止时间: 2020-01-01 至 2021-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=710467
• 关键词: Design; techniques; three; dimensional; integrated

The ever growing need for more complex integrated circuit (IC) has been driven by the need of complex new products packing more features and requiring faster and lower power processing. Scaling down transistors and using larger dies have been able to keep up with the market demand in the past. However, we are fast approaching the limits of continuous device scaling for planar two-dimensional (2D) IC design. Using 2D integration technologies to implement nowadays complex chips is becoming very expensive and difficult to meet nowadays design challenges. Three-dimensional (3D) integrated circuit (IC) technology, wherein IC chips are stacked in vertical 3D architectures, has emerged as a complement to silicon transistor scaling to achieve higher level of integration. Moreover, heterogeneous 3D-IC systems that integrate multiple dies, each optimized using different technologies, will offer More-than-Moore solutions for higher integration densities, lower power consumption, and higher performance. One of the most popular technologies for implementing 3D-ICs is through-silicon via (TSV) fabrication, in which multi-chip integration is enabled using TSVs to provide the vertical interconnections between dies. TSVs are smaller than off-chip wires thereby avoiding the excessive delay limitations of bonding wires. They can be used for connecting devices that reside on different dies, inter-die communications, as well as clock and power distribution. Like any new technology and despite the tremendous advantages of 3D-IC, circuits designer are faced with new design challenges particularly for clock synchronization and power delivery. The main design challenges are related to delay through the TSVs, which are susceptible to process and temperature variations. In addition, the delay through a TSV can increase significantly due to open defects leading to significant skew in clock distribution networks. Moreover, cross-die process variation limits the slack time for both within die and die-to-die paths using TSVs, thus requiring a tight constraint on clock skew and jitter . Intra-die and inter-die power distribution is another major challenge in 3D-IC design. Moreover, accurate physical characterization of TSVs represents a tremendous challenge for analog designer and an optimized layout technique is necessary to fully benefit from the advanced technology. As a result to fully enjoy the merit of 3D-IC technology, the objective of this proposal is to develop novel digital, analog and mixed signal circuit design and system techniques to address the challenges of 3D integrations.

对更复杂的集成电路 (IC) 的需求不断增长，这是由于对包含更多功能的复杂新产品的需求以及更快、更低功耗的处理的需求推动的。过去，缩小晶体管尺寸和使用更大芯片已经能够满足市场需求。然而，我们正在快速接近平面二维 (2D) IC 设计连续器件缩放的极限。使用 2D 集成技术来实现当今复杂的芯片变得非常昂贵并且难以应对当今的设计挑战。 三维 (3D) 集成电路 (IC) 技术（其中 IC 芯片以垂直 3D 架构堆叠）已成为硅晶体管微缩的补充，以实现更高的集成度。此外，集成多个芯片（每个芯片均使用不同技术进行优化）的异构 3D-IC 系统将提供超越摩尔解决方案，以实现更高的集成密度、更低的功耗和更高的性能。实现 3D-IC 最流行的技术之一是硅通孔 (TSV) 制造，其中使用 TSV 提供芯片之间的垂直互连，从而实现多芯片集成。 TSV 比片外引线更小，从而避免了键合引线的过度延迟限制。它们可用于连接位于不同芯片上的设备、芯片间通信以及时钟和电源分配。 与任何新技术一样，尽管 3D-IC 具有巨大的优势，但电路设计人员仍面临着新的设计挑战，特别是在时钟同步和功率传输方面。主要的设计挑战与 TSV 的延迟有关，它容易受到工艺和温度变化的影响。此外，由于开路缺陷会导致时钟分配网络出现严重偏差，因此通过 TSV 的延迟可能会显着增加。此外，跨裸片工艺变化限制了使用 TSV 的裸片内和裸片到裸片路径的松弛时间，因此需要严格限制时钟偏差和抖动。芯片内和芯片间电源分配是 3D-IC 设计中的另一个主要挑战。 此外，TSV 的准确物理特性对模拟设计人员来说是一个巨大的挑战，并且需要优化的布局技术才能充分受益于先进技术。 为了充分享受 3D-IC 技术的优点，本提案的目标是开发新颖的数字、模拟和混合信号电路设计和系统技术，以应对 3D 集成的挑战。