Design techniques for three-dimensional integrated circuits challenges

应对三维集成电路挑战的设计技术

• 批准号: RGPIN-2017-04292
• 负责人: ElSankary, Kamal
• 金额: $ 1.75万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2019
• 资助国家: 加拿大
• 起止时间: 2019-01-01 至 2020-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=679629
• 关键词: Design; techniques; three; dimensional; integrated

The ever growing need for more complex integrated circuit (IC) has been driven by the need of complex new products packing more features and requiring faster and lower power processing. Scaling down transistors and using larger dies have been able to keep up with the market demand in the past. However, we are fast approaching the limits of continuous device scaling for planar two-dimensional (2D) IC design. Using 2D integration technologies to implement nowadays complex chips is becoming very expensive and difficult to meet nowadays design challenges. ***Three-dimensional (3D) integrated circuit (IC) technology, wherein IC chips are stacked in vertical 3D architectures, has emerged as a complement to silicon transistor scaling to achieve higher level of integration. Moreover, heterogeneous 3D-IC systems that integrate multiple dies, each optimized using different technologies, will offer More-than-Moore solutions for higher integration densities, lower power consumption, and higher performance. One of the most popular technologies for implementing 3D-ICs is through-silicon via (TSV) fabrication, in which multi-chip integration is enabled using TSVs to provide the vertical interconnections between dies. TSVs are smaller than off-chip wires thereby avoiding the excessive delay limitations of bonding wires. They can be used for connecting devices that reside on different dies, inter-die communications, as well as clock and power distribution. ***Like any new technology and despite the tremendous advantages of 3D-IC, circuits designer are faced with new design challenges particularly for clock synchronization and power delivery. The main design challenges are related to delay through the TSVs, which are susceptible to process and temperature variations. In addition, the delay through a TSV can increase significantly due to open defects leading to significant skew in clock distribution networks. Moreover, cross-die process variation limits the slack time for both within die and die-to-die paths using TSVs, thus requiring a tight constraint on clock skew and jitter . Intra-die and inter-die power distribution is another major challenge in 3D-IC design. ***Moreover, accurate physical characterization of TSVs represents a tremendous challenge for analog designer and an optimized layout technique is necessary to fully benefit from the advanced technology.***As a result to fully enjoy the merit of 3D-IC technology, the objective of this proposal is to develop novel digital, analog and mixed signal circuit design and system techniques to address the challenges of 3D integrations.

对更复杂的集成电路（IC）的需求不断增长，这是由于需要包装更多功能并需要更快，更低的功率处理的复杂新产品所驱动的。缩小晶体管并使用更大的模具已经能够跟上过去的市场需求。但是，我们正在快速接近平面二维（2D）IC设计的连续设备缩放的限制。如今，使用2D集成技术实施复杂的芯片变得非常昂贵且难以应对设计挑战。 ***三维（3D）集成电路（IC）技术，其中IC芯片堆叠在垂直3D架构中，已成为硅晶体管缩放的补充，以达到更高的集成水平。此外，整合多个模具的异质3D-IC系统，每个模具都使用不同的技术进行了优化，将为高度集成密度，较低的功耗和更高的性能提供更多的解决方案。实施3D-IC的最受欢迎的技术之一是通过（TSV）制造通过Silicon，其中使用TSV启用了多芯片集成，以提供模具之间的垂直互连。 TSV小于芯片电线，从而避免了粘合线的过度延迟限制。它们可用于连接驻留在不同模具，间际通信以及时钟和电源分配的设备。 ***像任何新技术一样，尽管3D-IC具有巨大的优势，但电路设计师还是面临着新的设计挑战，尤其是对于时钟同步和动力传递而言。主要的设计挑战与延迟通过TSV有关，TSV容易受到过程和温度变化的影响。此外，由于打开缺陷，通过TSV的延迟会大大增加，从而导致时钟分布网络的偏斜偏移。此外，交叉过程的变化限制了使用TSV在Die和Die-Die路径内的松弛时间，因此需要对时钟偏斜和抖动的严格约束。 Intra Intra Intra Intra Inter-Die发电机分配是3D-IC设计中的另一个主要挑战。 ***此外，TSV的准确物理表征对模拟设计师来说是一个巨大的挑战，并且需要优化的布局技术才能完全受益于先进技术。该建议的目的是开发新颖的数字，模拟和混合信号电路设计和系统技术，以应对3D集成的挑战。