Digital and Memory Circuits in nano-scale CMOS Technologies

纳米级 CMOS 技术中的数字和存储电路

• 批准号: 205034-2012
• 负责人: Sachdev, Manoj
• 金额: $ 5.1万
• 依托单位: University of Waterloo
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2013
• 资助国家: 加拿大
• 起止时间: 2013-01-01 至 2014-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=523580
• 关键词: Digital; Memory; Circuits; nano; scale

Realization of robust integrated circuits in state of the art technologies is becoming increasingly difficult. The technology scaling makes transistors susceptible to process variations, and improper functioning of a single transistor may lead to the chip failure containing several million transistors. Often small as possible transistor sizes are used to reduce power, energy consumption, and to increase the packing density. Unfortunately, transistors with smaller dimensions exhibit a higher susceptibility to process variation. In particular, low-voltage, low-power Static Random Access Memory (SRAM) circuits show higher degree of variation owing to smallest possible transistor dimensions. In this research, we will investigate variability-aware design of digital, SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) - power, energy, yield, quality, and reliability are influenced by SRAMs.

以最先进的技术实现鲁棒的集成电路变得越来越困难。技术缩放使得晶体管容易受到工艺变化的影响，单个晶体管的不正常运行可能会导致包含数百万个晶体管的芯片故障。通常使用尽可能小的晶体管尺寸来降低功率、能耗并增加封装密度。 不幸的是，尺寸较小的晶体管对工艺变化的敏感性更高。特别是，低电压、低功耗静态随机存取存储器 (SRAM) 电路由于尽可能小的晶体管尺寸而表现出更高程度的变化。在这项研究中，我们将研究功率和电压受限环境中数字 SRAM 电路的可变性设计。在微处理器中，高达 70-80% 的晶体管位于 SRAM 中。因此，片上系统 (SoC) 的各个方面 - 功率、能源、产量、质量和可靠性都会受到 SRAM 的影响。