Exploring Memory and Digital Circuit Boundaries for Energy Efficient Hardware

探索节能硬件的内存和数字电路边界

• 批准号: RGPIN-2017-05044
• 负责人: Sachdev, Manoj
• 金额: $ 3.42万
• 依托单位: University of Waterloo
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2019
• 资助国家: 加拿大
• 起止时间: 2019-01-01 至 2020-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=689474
• 关键词: Exploring; Memory; Digital; Circuit; Boundaries

Impact of transistor scaling are evident everywhere. Often small as possible transistors are used to reduce the power, energy consumption, and to increase the packing density. Transistors with smaller dimensions exhibit a higher susceptibility to process variation. As a result, realization of robust, reliable circuit design becomes a challenge. In particular, SRAM circuits, and low-power, low-voltage digital circuits show higher degree of variation owing to smallest possible transistor dimensions, and low-supply voltage requirements. In this research, we will investigate variability-aware design of digital and SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) power, energy, yield, quality, and reliability are influenced by SRAMs.***This research proposal has two major components (i) SRAMs, and (ii) Logic circuits. Key research objectives for the SRAM are: (a) lower SRAM power consumption with architectural, circuit innovation to realize a reliable, ultra-low-voltage SRAMs. In particular, devise circuit techniques to alleviate the impact of process variations on important SRAM blocks such as sense amplifiers, SRAM cells, and (b) mitigate the impact of soft errors and weak failures through hardened by design and efficient implementation Error Correcting Codes (ECC) which may further improve low-voltage SRAM operation. The key research objective for logic circuits is ultra-low-voltage, energy efficient logic family and to realize ultra-low-voltage digital building blocks. The long term (5 years) objective of this research is to put all these ideas together in silicon to (a) fabricate fully functional ultra-low-voltage; low-power SRAMs in 28 nm CMOS technology; (b) design and fabricate soft error robust low-power SRAMs; (c) design and fabricate a low-power, low-voltage digital circuits such as 32/64b adder capable of working at 100 mV. In all instances, test chips will be manufactured, and measurements will be carried out.**

晶体管尺寸缩小的影响随处可见。通常使用尽可能小的晶体管来降低功率、能耗并增加封装密度。 尺寸较小的晶体管对工艺变化的敏感性更高。因此，实现稳健、可靠的电路设计成为一项挑战。特别是，由于尽可能小的晶体管尺寸和低电源电压要求，SRAM 电路和低功耗、低电压数字电路表现出更高程度的变化。在这项研究中，我们将研究功率和电压受限环境中数字和 SRAM 电路的可变性设计。在微处理器中，高达 70-80% 的晶体管位于 SRAM 中。因此，片上系统 (SoC) 的功率、能源、良率、质量和可靠性的各个方面都会受到 SRAM 的影响。***本研究提案有两个主要组成部分 (i) SRAM，以及 (ii) 逻辑电路。 SRAM 的主要研究目标是： (a) 通过架构、电路创新降低 SRAM 功耗，以实现可靠的超低电压 SRAM。特别是，设计电路技术来减轻工艺变化对重要 SRAM 块（例如读出放大器、SRAM 单元）的影响，以及 (b) 通过强化设计和高效实施纠错码 (ECC) 来减轻软错误和弱故障的影响）这可以进一步改善低压SRAM操作。逻辑电路的重点研究目标是超低电压、高能效逻辑系列并实现超低电压数字构件。这项研究的长期（5 年）目标是将所有这些想法整合到硅中，以 (a) 制造功能齐全的超低电压；采用 28 nm CMOS 技术的低功耗 SRAM； (b) 设计和制造软错误稳健的低功耗 SRAM； (c)设计并制作低功耗、低电压数字电路，例如能够工作在100 mV的32/64b加法器。在所有情况下，都将制造测试芯片并进行测量。**