Digital and Memory Circuits in nano-scale CMOS Technologies

纳米级 CMOS 技术中的数字和存储电路

• 批准号: 205034-2012
• 负责人: Sachdev, Manoj
• 金额: $ 5.1万
• 依托单位: University of Waterloo
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2015
• 资助国家: 加拿大
• 起止时间: 2015-01-01 至 2016-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=570035
• 关键词: Digital; Memory; Circuits; nano; scale

Realization of robust integrated circuits in state of the art technologies is becoming increasingly difficult. The technology scaling makes transistors susceptible to process variations, and improper functioning of a single transistor may lead to the chip failure containing several million transistors. Often small as possible transistor sizes are used to reduce power, energy consumption, and to increase the packing density. Unfortunately, transistors with smaller dimensions exhibit a higher susceptibility to process variation. In particular, low-voltage, low-power Static Random Access Memory (SRAM) circuits show higher degree of variation owing to smallest possible transistor dimensions. In this research, we will investigate variability-aware design of digital, SRAM circuits in power and voltage constrained environments. In microprocessors up to 70-80% of transistors are in SRAMs. As a consequence, various aspects of Systems on Chip (SoC) - power, energy, yield, quality, and reliability are influenced by SRAMs. The proposed research has two broad segments - (a) SRAM circuits, and (b) logic circuits. In the first segment, few aspects of SRAMs will be investigated. The key objectives of this research are (i) to lower SRAM power consumption through architectural and circuit innovation. We will design functional SRAMs working at sub-threshold voltages. (ii) To devise circuit techniques to alleviate the impact of process variations on important SRAM blocks such as the sense amplifier. We will investigate new architectures and circuits for the sense amplifier. (iii) Design soft error robust SRAM cells that can recover from single event upsets. In the second segment of the research, we will investigate high speed digital circuits working at the nominal voltage. Research on high speed circuits will entail investigation of high speed logic styles. This work builds on our recent research on Constant Delay (CD) logic style. Building blocks such as adder will be designed to demonstrate effectiveness of new logic families for high-speed applications.

以最先进的技术实现鲁棒的集成电路变得越来越困难。技术缩放使得晶体管容易受到工艺变化的影响，单个晶体管的不正常运行可能会导致包含数百万个晶体管的芯片故障。通常使用尽可能小的晶体管尺寸来降低功率、能耗并增加封装密度。 不幸的是，尺寸较小的晶体管对工艺变化的敏感性更高。特别是，低电压、低功耗静态随机存取存储器 (SRAM) 电路由于尽可能小的晶体管尺寸而表现出更高程度的变化。在这项研究中，我们将研究功率和电压受限环境中数字 SRAM 电路的可变性设计。在微处理器中，高达 70-80% 的晶体管位于 SRAM 中。因此，片上系统 (SoC) 的各个方面 - 功率、能源、产量、质量和可靠性都会受到 SRAM 的影响。 拟议的研究有两个主要部分 - (a) SRAM 电路和 (b) 逻辑电路。在第一部分中，将研究 SRAM 的几个方面。这项研究的主要目标是 (i) 通过架构和电路创新降低 SRAM 功耗。我们将设计工作在亚阈值电压下的功能性 SRAM。 (ii) 设计电路技术来减轻工艺变化对重要 SRAM 模块（例如读出放大器）的影响。我们将研究传感放大器的新架构和电路。 (iii) 设计能够从单事件干扰中恢复的软错误鲁棒 SRAM 单元。在研究的第二部分中，我们将研究在标称电压下工作的高速数字电路。对高速电路的研究将需要对高速逻辑类型的研究。这项工作建立在我们最近对恒定延迟 (CD) 逻辑风格的研究之上。加法器等构建模块将被设计为展示新逻辑系列对于高速应用的有效性。