Developement of Contactless and Non-Destructive Capacitance-Voltage Measurement System in Ultra-High Vacuum

超高真空非接触式无损电容电压测量系统的研制

基本信息

批准号：
08555072
负责人：
HASEGAWA Hideki
金额：
$ 3.84万
依托单位：
HOKKAIDO UNIVERSITY
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (A)
财政年份：
1996
资助国家：
日本
起止时间：
1996 至 1997
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-08555072/
关键词：
contactless C-V UHV-based system surface state interface state Fermi level pinning hydrogen-terminated surface ultrathin insulator ECR plasma oxynitride film 非接触C-V 半導体自由表面極薄絶縁膜トンネル絶縁膜原子スケール表面制御

项目摘要

The purpose if this rsearch is to develop the "Contactless and Non-Destructive Capacitance-Voltage (C-V) Measurement System" for characterization of a conduction type, an impurity profile and a surface state density distribution of semiconductor materials in ultra-high vacuum (UHV) environment and to study various types of semiconductor surfaces such as reconstructed surfaces, processed surfaces, surfaces covered with ultrathin insulating films, etc. The main results obtained are listed below :(1) The system consists of four parts as follows : (a) An UHV chamber with a sample transfer system and a pump system, (b) a field plate which can maintain a parallelism and a constant distance of 100-300nm from a sample surface by piezo-mechanism with a capacitance feedback, (c) a UHV gap measurement part based on the optical method utilizing change in reflectivity due to penetration of evanescent wave (the Goos-Haenchen effect) and (d) a controller including C-V meter. The base pressure of the … More chamber was within the range of 10^<-10> Torr. The resolutions of a measured capacitance of 0.2fF and a UHV gap distance of 1nm were achieved, respectively.(2) The validity of the system was checked by using a SiO_2/Si metal oxide semiconductor (MOS) system. The obtained contactless C-V curve was well in agreement with the calculated ideal C-V curve.(3) The hydrogen-terminated Si surfaces showed the Fermi level pinning phenomena due to a high density of discrete surface state lying at 0.6eV above the valence band.(4) It was found that the Si surfaces covered with ultrathin oxides formed by chemical and thermal processes at temperatures below 400ﾟC had high-density interface states with narrow U-shaped continuous distributions, resulting in the Fermi level pinning near the hybrid orbital charge neutrality level.(5)The oxynitrided Si surface by ECR N_2O plasma was found to be pinning free, showing a wide, U-shaped, continuous interface state distribution with a minimum value of 1.0_x10^<11> eV^<-1>cm^<-2>. The formation of phase-separated Si_3N_4/SiO_2 interfacial structure was responsible for realization of the pinning free interface.(6) Contactless C-V results directly showed strong surface Fermi level pinning at the molecular-beam-epitaxy (MBE) grown GaAs (001) (2x4) surfaces, and the observed pinning behavior cannot be explained by the "kink-acceptor model". Less

这项研究的目的是开发“非接触式、非破坏性电容电压（C-V）测量系统”，用于表征超高真空（UHV）半导体材料的导电类型、杂质分布和表面态密度分布）环境下对各种类型的半导体加工表面进行研究，如重构表面、表面、覆盖超薄绝缘膜的表面等。获得的主要结果如下：（1）系统由四部分组成如下：(a) 带有样品传输系统和泵系统的 UHV 室，(b) 场板，可通过具有电容反馈的压电机制保持平行度和与样品表面 100-300 nm 的恒定距离，（c）基于光学方法的UHV间隙测量部分，利用由于倏逝波的穿透（古斯-哈恩兴效应）引起的反射率变化，以及（d）包括C-V计的控制器。腔室的分辨率在10^<-10>Torr范围内，测量电容分辨率分别为0.2fF，UHV间隙距离为1nm。(2)通过以下方法检查系统的有效性。使用SiO_2/Si金属氧化物半导体(MOS)系统获得的非接触C-V曲线与计算的理想C-V曲线非常吻合。(3)氢封端的Si表面显示出由于位于价带上方 0.6eV 的高密度离散表面态，导致费米能级钉扎现象。(4) 研究发现，在 400°C 以下的温度下，通过化学和热过程形成的超薄氧化物覆盖的 Si 表面具有很高的费米能级钉扎现象。 -具有窄U形连续分布的密度界面态，导致费米能级钉扎在混合轨道电荷中性能级附近。(5)ECR N_2O等离子体的氮氧化Si表面发现是无钉扎的，呈现出宽的、U形的、连续的界面态分布，其最小值为1.0_x10^<11>eV^<-1>cm^<-2>相分离的Si_3N_4的形成。 /SiO_2界面结构负责实现无钉扎界面。(6)非接触C-V结果直接显示了分子束外延的强表面费米能级钉扎(MBE) 生长的 GaAs (001) (2x4) 表面，并且观察到的钉扎行为不能用“扭结受体模型”来解释。