Collaborative Research: SHF: Medium: Revitalizing EDA from a Machine Learning Perspective

合作研究：SHF：媒介：从机器学习的角度振兴 EDA

• 批准号: 2106828
• 负责人: Yiran Chen
• 金额: $ 41万
• 依托单位: Duke University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2021
• 资助国家: 美国
• 起止时间: 2021-10-01 至 2025-09-30
• 项目状态: 未结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=2106828&HistoricalAwards=false
• 关键词: Collaborative; Research; SHF; Medium; Revitalizing

Despite its spectacular success in the past, design automation of electronic circuits and systems remains limited in effectiveness and efficiency. This is often due to unnecessarily excessive iterations of point software tools, where early predictions on downstream design steps are overly pessimistic and interoperations among different tools largely require manual handling. As such, existing chip-design flows are not considered fully automated, and there still exists a strong need for jointly exploring the considerable room between the different steps in these flows. Moreover, existing design-verification approaches usually involve unwanted redundancy and substantial manual effort, contributing greatly to a well-known bottleneck of time-to-market. The recent progress in machine-learning technology offers a great opportunity to revitalize current Electronic Design Automation (EDA) flows from an alternative perspective, i.e., extracting design and verification knowledge from existing design data, and reusing it on new designs. The goal of this research is to develop such knowledge extraction and reuse techniques with the aid of the state-of-the-art machine learning technology. The outcome of this research is to help mitigate the chip-design productivity crisis and cater to the increasing demand for hardware-accelerated computing. This research is also training students, including women and under-represented minorities, with interdisciplinary skills and preparing tomorrow’s high-tech workforce in the U.S. for solving challenges in the electronic industry.The project involves systematic research on machine learning in the context of electronic design automation with five integrated components: 1) development of learning-based fast and high fidelity prediction techniques for knowledge extraction in the structural and behavioral domains of circuit designs; 2) a study on how to seamlessly integrate the design predictions with circuit optimizations; 3) applying machine-learning prediction to accelerating functional-verification coverage and facilitating automated debugging; 4) developing autonomous learning on the interplay amongst tools and thereby achieving automated synthesis space exploration; 5) automated machine-learning architecture search and feature refinement in EDA applications.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

尽管电子电路和系统的设计自动化在过去取得了巨大的成功，但其有效性和效率仍然有限，这通常是由于点软件工具的不必要的过度迭代，其中对下游设计步骤的早期预测过于悲观以及不同工具之间的互操作。因此，现有的芯片设计流程并不被认为是完全自动化的，并且仍然强烈需要共同探索这些流程中不同步骤之间的相当大的空间。此外，现有的设计验证方法通常涉及不需要的内容。冗余机器学习技术的最新进展为从另一种角度（即提取）振兴当前的电子设计自动化（EDA）流程提供了绝佳的机会。这项研究的目标是借助最先进的机器学习技术来开发此类知识提取和重用技术。研究是为了帮助缓解这项研究还对学生（包括女性和代表性不足的少数族裔）进行跨学科培训，并为美国未来的高科技劳动力解决技术挑战做好准备。该项目涉及电子设计自动化背景下的机器学习系统研究，具有五个集成组件：1）开发基于学习的快速高保真预测技术，用于电路设计结构和行为领域的知识提取； 2) 研究如何将设计预测与电路优化无缝集成；3）应用机器学习预测来加速功能验证覆盖范围并促进自动化调试；4）开发工具间相互作用的自主学习，从而实现自动化综合空间探索； EDA 应用中的机器学习架构搜索和功能细化。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning

您的 Verilog RTL 代码有多好？：机器学习的快速解答

• DOI: 10.1145/3508352.3549375
• 发表时间: 2022-10-30
• 期刊: Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design
• 作者: Prianka Sengupta;Aakash Tyagi;Yiran Chen;Jiangkun Hu
• 通讯作者: Jiangkun Hu

Automatic Routability Predictor Development Using Neural Architecture Search

使用神经架构搜索开发自动可路由性预测器

• DOI: 10.1109/iccad51958.2021.9643483
• 发表时间: 2021-11
• 期刊: International Conference on Computer-Aided Design (ICCAD
• 作者: Chang, Chen;Pan, Jingyu;Zhang, Tunhou;Xie, Zhiyao;Hu, Jiang;Qi, Weiyi;Lin, Chun;Liang, Rongjian;Mitra, Joydeep;Fallon, Elias;et al
• 通讯作者: et al

APOLLO: An Automated Power Modeling Framework for Runtime Power Introspection in High-Volume Commercial Microprocessors

APOLLO：用于大容量商用微处理器运行时功耗自省的自动功耗建模框架

• DOI: 10.1145/3466752.3480064
• 发表时间: 2021-10
• 期刊: IEEE/ACM International Symposium on Microarchitecture (MICRO
• 作者: Xie, Zhiyao;Xu, Xiaoqing;Walker, Matt;Knebel, Joshua;Palaniswamy, Kumaraguru;Hebert, Nicolas;Hu, Jiang;Yang, Huanrui;Chen, Yiran;Das, Shidhartha
• 通讯作者: Das, Shidhartha

The Dark Side: Security and Reliability Concerns in Machine Learning for EDA

黑暗面：EDA 机器学习的安全性和可靠性问题

• DOI: 10.1109/tcad.2022.3199172
• 发表时间: 2023-04-01
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Zhiyao Xie;Jingyu Pan;Chen;Jiangkun Hu;Yiran Chen
• 通讯作者: Yiran Chen

Preplacement Net Length and Timing Estimation by Customized Graph Neural Network

通过定制图神经网络进行预置网络长度和时序估计

• DOI: 10.1109/tcad.2022.3149977
• 发表时间: 2022-11-01
• 期刊: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
• 影响因子: 2.9
• 作者: Zhiyao Xie;Rongjian Liang;Xiaoqing Xu;Jiangkun Hu;Chen;Jingyu Pan;Yiran Chen
• 通讯作者: Yiran Chen