Collaborative Research: Two-dimensional Synaptic Array for Advanced Hardware Acceleration of Deep Neural Networks

合作研究：用于深度神经网络高级硬件加速的二维突触阵列

• 批准号: 1955246
• 负责人: Yiran Chen
• 金额: $ 20万
• 依托单位: Duke University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2020
• 资助国家: 美国
• 起止时间: 2020-09-01 至 2024-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1955246&HistoricalAwards=false
• 关键词: Collaborative; Research; Two; dimensional; Synaptic

Nontechnical:The big data revolution has created a critical need for new computing paradigms to efficiently extract valuable information from large datasets. In existing computing systems, data is constantly transferred between the computation and memory units. This so-called memory bottleneck limits their energy efficiency and speed. In contrast, computation and memory in the human brain (neurons and synapses) are closely and densely interconnected. This gives rise to the brain’s extremely low power consumption at ~20W. Inspired by the brain, neuromorphic computing and artificial neural networks have recently attracted immense interest. In particular, deep neural networks (DNNs) can execute complex processing tasks such as pattern recognition and image reconstruction. However, DNNs are computationally intensive and power hungry. This makes it impractical for them to be scaled up to the level of the complexity for true artificial intelligence (AI). In this project, the team will develop a novel artificial synapse for deep neural networks. This prototypical synapse will offer low power consumption, high precision, good scalability, and great potential for large-scale integration. This work can lead to significant improvement in energy efficiency, bandwidth, and performance for deep learning algorithms. The research outcome can lead to the wide use of AI for both high-performance computing and low-power flexible electronics. This project can revolutionize society through advances in healthcare, self-driving vehicles, and autonomous manufacturing. The team will work closely with their local communities to attract students to pursue engineering careers, especially those from underrepresented groups. Activities will include laboratory demonstrations, design projects, summer internships, and career workshops.Technical:The objective of this project is to develop scalable electrochemical two-dimensional (2D) synaptic arrays with high-precision and low-power for advanced hardware acceleration of deep neural networks (DNNs) with orders of magnitude improvements in energy and speed. While binary SRAM cells have shown promising performance for DNN hardware acceleration, its inherent limitations in power and area make it impractical to scale up to the complexity level required for large-scale problems and/or datasets. In this project, the team will take a holistic approach to develop scalable electrochemical 2D synaptic arrays with high precision, lower-power, good linearity, low variations, and CMOS compatibility for large-scale integration. The team will carry out the following three research tasks: (1) device-level optimization in device precision, dynamic range, and scaling; (2) array-level demonstration by building synaptic arrays, lowering device variations, and designing peripheral circuits; (3) system-level integration via building device models, implementing computing-in-memory (CIM), and demonstrating on-chip learning for pixel-to-pixel applications. This work will provide a low-power and scalable framework for the hardware acceleration of DNNs, paving the ways towards the ubiquitous use of artificial intelligence (AI) in both high-performance computers and low-power embedded systems.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

非技术性：大数据革命迫切需要新的计算范式，以从大型数据集中有效地提取有价值的信息。在现有的计算系统中，数据在计算和内存单元之间不断传输，这种所谓的内存瓶颈限制了它们的能源效率。相比之下，人脑（神经元和突触）中的计算和记忆紧密相连，这使得大脑的功耗极低，约为 20W，这受到大脑神经形态计算的启发。人工神经网络最近引起了极大的兴趣，特别是深度神经网络（DNN）可以执行复杂的处理任务，例如模式识别和图像重建，但是，DNN 计算量大且耗电，这使得它们不切实际。在这个项目中，该团队将为深度神经网络开发一种新型人工突触，这种原型突触将提供低功耗、高精度、良好的可扩展性和出色的可扩展性。潜力这项工作可以显着提高深度学习算法的能源效率、带宽和性能，从而推动人工智能在高性能计算和低功耗柔性电子领域的广泛应用。该项目可以通过医疗保健、自动驾驶汽车和自主制造方面的进步来彻底改变社会，该团队将与当地社区密切合作，吸引学生从事工程职业，特别是那些来自弱势群体的学生。活动将包括实验室演示、设计项目、暑期实习和职业技术：该项目的目标是开发高精度、低功耗的可扩展电化学二维 (2D) 突触阵列，用于深度神经网络 (DNN) 的高级硬件加速，在能量和速度方面实现数量级的改进虽然二进制 SRAM 单元在 DNN 硬件加速方面表现出了良好的性能，但其在功耗和面积方面的固有限制使其无法扩展到大规模问题和/或数据集所需的复杂性级别。该团队将开展以下三项研究任务：（1）器件级优化。器件精度、动态范围和缩放；（2）通过构建突触阵列、降低器件变化和设计外围电路进行阵列级演示；（3）通过构建器件模型、实现内存计算进行系统级集成； （CIM），并演示像素到像素应用的片上学习。这项工作将为 DNN 的硬件加速提供一个低功耗且可扩展的框架，为人工智能 (AI) 的普遍使用铺平道路。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

ReTransformer: ReRAM-based processing-in-memory architecture for transformer acceleration

ReTransformer：基于 ReRAM 的内存处理架构，用于 Transformer 加速

• DOI: 10.1145/3400302.3415640
• 发表时间: 2020-11
• 期刊: IEEE/ACM International Conference on Computer-Aided Design (ICCAD
• 作者: Yang, Xiaoxuan;Yan, Bonan;Li, Hai;Chen, Yiran
• 通讯作者: Chen, Yiran

DefT: Boosting Scalability of Deformable Convolution Operations on GPUs

DefT：提高 GPU 上可变形卷积运算的可扩展性

• DOI: 10.1145/3582016.3582017
• 发表时间: 2023-03-25
• 期刊: Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 3
• 作者: Edward Hanson;Mark Horton;H. Li;Yiran Chen
• 通讯作者: Yiran Chen

Improving the Robustness and Efficiency of PIM-Based Architecture by SW/HW Co-Design

通过软件/硬件协同设计提高基于 PIM 的架构的稳健性和效率

• DOI: 10.1145/3566097.3568358
• 发表时间: 2023-01
• 期刊: 2023 28th Asia and South Pacific Design Automation Conference (ASP-DAC
• 作者: Yang, Xiaoxuan;Li, Shiyu;Zheng, Qilin;Chen, Yiran
• 通讯作者: Chen, Yiran

Cascading structured pruning: enabling high data reuse for sparse DNN accelerators

级联结构化剪枝：实现稀疏 DNN 加速器的高数据重用

• DOI: 10.1145/3470496.3527419
• 发表时间: 2022-06
• 期刊: International Symposium on Computer Architecture (ISCA
• 作者: Hanson, Edward;Li, Shiyu;Li, Hai 'Helen';Chen, Yiran
• 通讯作者: Chen, Yiran

SpikeSen: Low-Latency In-Sensor-Intelligence Design With Neuromorphic Spiking Neurons

SpikeSen：具有神经形态尖峰神经元的低延迟传感器内智能设计

• DOI: 10.1109/tcsii.2023.3235888
• 发表时间: 2023-06
• 期刊: IEEE Transactions on Circuits and Systems II: Express Briefs
• 作者: Li, Ziru;Zheng, Qilin;Chen, Yiran;Li, Hai
• 通讯作者: Li, Hai