SaTC: CORE: Small: Towards Smart and Secure Non Volatile Memory

SaTC：核心：小型：迈向智能、安全的非易失性存储器

• 批准号: 1717550
• 负责人: Huiyang Zhou
• 金额: $ 47.44万
• 依托单位: North Carolina State University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2017
• 资助国家: 美国
• 起止时间: 2017-07-31 至 2021-07-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1717550&HistoricalAwards=false
• 关键词: SaTC; CORE; Small; Towards; Smart

Non-volatile memory (NVM) technologies and the 3D-integration technology reshape memory systems. Although providing many desirable features such as low leakage power and fast system restart, the non-volatility of NVM introduces the vulnerability to data remanence attacks. This project leverages the processing-in-memory (PIM), enabled by vertically stacked 3D integration of integrated circuits, to overcome the security challenge associated with NVM.In this project, we use an attack model, in which an attacker can physically obtain the NVM chip and scan the data stored in NVM, can also snoop on the memory bus to retrieve data and addresses; and can tamper with the memory content as well as commands. Our trust base includes both the processor and the memory chip, meaning that the hardware logic and state registers inside the chips are well hidden from the attacker. To protect against data scanning and memory bus snooping, we utilize counter-mode encryption to encrypt data and obfuscate addresses. The data stored in NVM are always encrypted while the addresses are encrypted at the processor side and decrypted at the memory side. The decryption logic becomes a part of the PIM logic on NVM chips. To protect against data tampering, we develop efficient integrity checks by re-purposing error correction codes (ECC) for integrity checking such that the existing error correction logic can be used for both error detection/correction and integrity verification. Overall, we leverage PIM to protect data and access patterns and ensure the data integrity. The end result of the project is smart and secure NVM architecture designs.

非易失性存储器（NVM）技术和3D集成技术重塑了存储系统。尽管提供了许多理想的功能，例如低泄漏功率和快速系统重启，但 NVM 的非易失性导致了数据剩磁攻击的脆弱性。该项目利用通过垂直堆叠集成电路 3D 集成实现的内存处理 (PIM) 来克服与 NVM 相关的安全挑战。在该项目中，我们使用攻击模型，攻击者可以在其中物理获取NVM芯片并扫描NVM中存储的数据，还可以窥探内存总线以检索数据和地址；并可以篡改内存内容和命令。我们的信任基础包括处理器和存储芯片，这意味着芯片内的硬件逻辑和状态寄存器对攻击者来说是隐藏的。为了防止数据扫描和内存总线窥探，我们利用计数器模式加密来加密数据并混淆地址。 NVM中存储的数据始终是加密的，而地址在处理器侧加密并在存储器侧解密。解密逻辑成为NVM芯片上PIM逻辑的一部分。为了防止数据篡改，我们通过重新利用纠错码（ECC）进行完整性检查来开发有效的完整性检查，以便现有的纠错逻辑可以用于错误检测/纠正和完整性验证。总的来说，我们利用 PIM 来保护数据和访问模式并确保数据完整性。该项目的最终结果是智能且安全的 NVM 架构设计。

项目成果

Reliability Modeling of NISQ- Era Quantum Computers

NISQ-时代量子计算机的可靠性建模

• DOI: 10.1109/iiswc50251.2020.00018
• 发表时间: 2020-10
• 期刊: IEEE International Symposium on Workload Characterization
• 作者: Liu, Ji;Zhou, Huiyang
• 通讯作者: Zhou, Huiyang

MKPipe: a compiler framework for optimizing multi-kernel workloads in OpenCL for FPGA

MKPipe：用于优化 OpenCL for FPGA 中的多内核工作负载的编译器框架

• DOI: 10.1145/3392717.3392757
• 发表时间: 2020-06
• 期刊: The 34th ACM International Conference on Supercomputing
• 作者: Liu, Ji;Kafi, Abdullah;Shen, Xipeng;Zhou, Huiyang
• 通讯作者: Zhou, Huiyang

Coordinated CTA Combination and Bandwidth Partitioning for GPU Concurrent Kernel Execution

GPU 并发内核执行的协调 CTA 组合和带宽分区

• DOI: 10.1145/3326124
• 发表时间: 2019-08
• 期刊: ACM Transactions on Architecture and Code Optimization
• 影响因子: 1.6
• 作者: Lin, Zhen;Dai, Hongwen;Mantor, Michael;Zhou, Huiyang
• 通讯作者: Zhou, Huiyang

Quantum Circuits for Dynamic Runtime Assertions in Quantum Computation

量子计算中动态运行时断言的量子电路

• DOI: 10.1109/lca.2019.2935049
• 发表时间: 2019-05-24
• 期刊: IEEE Computer Architecture Letters
• 影响因子: 2.3
• 作者: Huiyang Zhou;G. Byrd
• 通讯作者: G. Byrd

PSSM: achieving secure memory for GPUs with partitioned and sectored security metadata

PSSM：通过分区和扇区安全元数据实现 GPU 安全内存

• DOI: 10.1145/3447818.3460374
• 发表时间: 2021-06
• 期刊: The 35th ACM International Conference on Supercomputing
• 作者: Yuan, Shougang;Solihin, Yan;Zhou, Huiyang
• 通讯作者: Zhou, Huiyang