SHF: Small: Exploration of the Transistor-level Monolithic 3D SRAM Design Space

SHF：小型：晶体管级单片 3D SRAM 设计空间的探索

基本信息

批准号：
1714161
负责人：
Niraj Jha
金额：
$ 45万
依托单位：
Princeton University
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2017
资助国家：
美国
起止时间：
2017-09-01 至 2021-08-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1714161&HistoricalAwards=false
关键词：
SHF Small Exploration Transistor level

项目摘要

Static random-access memories (SRAMs) constitute an important part of modern microprocessors, occupying more than half of its area. They are part of the memory hierarchy that enables applications to be sped up on these processors. Since traditional 2D scaling of integrated circuits (ICs) is running out of steam, an alternative in the coming decade would be to go vertical, i.e., have several layers of logic and memory in the same IC package. There are two ways to go 3D: using through-silicon vias (TSVs) or monolithic 3D integration. Since monolithic 3D integration enjoys many advantages over TSV based 3D integration, this work is aimed at the former. In particular, its aim is to explore the design space of transistor-level monolithic (TLM) 3D SRAMs implemented in the modern semiconductor technology of FinFETs. A successful conclusion of this work, hence, should be very beneficial to the semiconductor industry. The designs/methodologies/tools that are developed will be made available on the web. They will also be disseminated to the industry through various companies the PI interacts with. The material will be included in a course that the PI teaches. Many seniors are expected to do their thesis on this topic. Female and minority PhD students will be attracted to this research through Princeton Fellowships available for this purpose. Further outreach activities are also planned for high-school students. Results will be disseminated through research articles and seminars.In the TLM design style, the n-type and p-type transistors can be placed on different layers, thus reducing the footprint area of an SRAM bitcell significantly. This also enables separate optimizations of the two layers, which has the added advantage of improving stability of SRAM cells. Stability is a very important metric for SRAMs since they push the semiconductor technology to its limits in order to accommodate as much memory into the microprocessor as possible. However, there is hardly any work on the TLM FinFET SRAM bitcell design space exploration. The proposed work fills this gap through accurate capacitance extraction and device simulation, under process-voltage-temperature variations on the IC.

静态随机存取存储器（SRAM）是现代微处理器的重要组成部分，占据了一半以上的面积。它们是内存层次结构的一部分，使应用程序能够在这些处理器上加速。由于传统的集成电路 (IC) 二维缩放已经失去动力，未来十年的替代方案将是垂直化，即在同一个 IC 封装中拥有多层逻辑和存储器。实现 3D 的方法有两种：使用硅通孔 (TSV) 或单片 3D 集成。由于单片 3D 集成比基于 TSV 的 3D 集成具有许多优势，因此这项工作针对的是前者。特别是，其目标是探索采用 FinFET 现代半导体技术实现的晶体管级单片 (TLM) 3D SRAM 的设计空间。因此，这项工作的成功完成应该对半导体行业非常有利。开发的设计/方法/工具将在网络上提供。它们还将通过 PI 与之互动的各个公司向业界传播。该材料将包含在 PI 教授的课程中。许多高年级学生预计将就此主题撰写论文。通过为此目的提供的普林斯顿奖学金，女性和少数族裔博士生将被吸引到这项研究中。还计划为高中生开展进一步的外展活动。结果将通过研究文章和研讨会进行传播。在 TLM 设计风格中，n 型和 p 型晶体管可以放置在不同的层上，从而显着减少 SRAM 位单元的占用面积。这还可以对两层进行单独优化，从而具有提高 SRAM 单元稳定性的额外优势。稳定性是 SRAM 的一个非常重要的指标，因为它们将半导体技术推向极限，以便将尽可能多的内存容纳到微处理器中。然而，几乎没有任何关于 TLM FinFET SRAM 位单元设计空间探索的工作。所提出的工作通过在 IC 的工艺电压-温度变化下进行精确的电容提取和器件模拟来填补这一空白。