SHF: Small: Parasitics-aware Exploration of the FinFET SRAM Design Space

SHF：小型：FinFET SRAM 设计空间的寄生感知探索

• 批准号: 1318603
• 负责人: Niraj Jha
• 金额: $ 45万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-09-01 至 2017-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1318603&HistoricalAwards=false
• 关键词: SHF; Small; Parasitics; aware; Exploration

Planar complementary metal-oxide-semiconductor (CMOS) technology scaling is coming to an end with the adoption of FinFETs (a type of field-effect transistor or FET) at the 22nm technology node and beyond. As a result of having multiple gates wrapped around the fin body, FinFETs exhibit better control of the channel potential with scaling, thereby alleviating the explosive leakage current problem faced by planar short-channel devices. Since static random access memory (SRAM) bit-cells are often the densest features patterned on an integrated circuit, researchers have begun investigating the design and manufacturability of FinFET SRAMs. Most of these investigations focus on enhancing/contrasting SRAM direct current (DC) metric targets. However, such metrics are not an accurate guide to FinFET bit-cell designers, as parasitic capacitances for two topologically equivalent bit-cells can be very different (due to differing fin pitches, etc.), resulting in widely varying transient characteristics. Thus, in order to predict array-scale metrics through simulation, capturing transient behavior accurately is absolutely essential. To accomplish the latter, SRAM parasitic capacitances need to be extracted accurately from the layout. Using an accurate parasitic capacitance extraction method that the principal investigator's (PI's) group has developed, the project plans to explore the FinFET SRAM design space from both DC metrics and transient behavior points of view, under process-voltage-temperature variations. Since SRAMs account for more than 50% of the area of modern microprocessors, it is very important to base them on the best SRAM bit-cell design. A successful conclusion of this work, hence, should be very beneficial to the semiconductor industry. The designs/methodologies/tools that are to be developed will be disseminated through the web. Technology transfer will be done through various companies the PI interacts with. The material will be included in a course on Design with Nanotechnologies that the PI teaches. Princeton has a tradition of undergraduate independent research. Many seniors are expected to do their research project on this topic. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program. The PI has supervised 10 female Ph.D. students so far. Further outreach activities are also planned for high-school students. The PI has supervised the research of four high-school students in the last two years, including a female student.

随着 22 纳米及更高技术节点采用 FinFET（一种场效应晶体管或 FET），平面互补金属氧化物半导体 (CMOS) 技术的微缩化即将结束。由于鳍体周围有多个栅极，FinFET 通过缩放可以更好地控制沟道电势，从而缓解平面短沟道器件面临的爆炸性漏电流问题。由于静态随机存取存储器 (SRAM) 位单元通常是集成电路上图案最密集的特征，因此研究人员已开始研究 FinFET SRAM 的设计和可制造性。这些研究大部分集中在增强/对比 SRAM 直流 (DC) 指标目标。然而，此类指标并不能准确指导 FinFET 位单元设计人员，因为两个拓扑等效的位单元的寄生电容可能非常不同（由于鳍片间距不同等），从而导致瞬态特性差异很大。因此，为了通过仿真预测阵列规模的指标，准确捕获瞬态行为绝对至关重要。为了实现后者，需要从布局中准确提取 SRAM 寄生电容。该项目计划使用首席研究员 (PI) 小组开发的精确寄生电容提取方法，从 DC 指标和瞬态行为的角度探索工艺电压温度变化下的 FinFET SRAM 设计空间。由于 SRAM 占现代微处理器面积的 50% 以上，因此将其基于最佳的 SRAM 位单元设计非常重要。因此，这项工作的成功完成应该对半导体行业非常有利。将要开发的设计/方法/工具将通过网络传播。技术转让将通过 PI 与之互动的各个公司来完成。该材料将包含在 PI 教授的纳米技术设计课程中。普林斯顿大学有本科生独立研究的传统。许多高年级学生预计将开展有关该主题的研究项目。普林斯顿大学总统奖学金计划将吸引女性和少数族裔学生参与这项研究。 PI已指导10名女性博士。到目前为止的学生。还计划为高中生开展进一步的外展活动。过去两年，PI 监督了四名高中生的研究，其中包括一名女学生。