SHF: Small: Efficient and Accurate Methodologies for Unifying the Layout, Device Simulation, and Process Simulation Worlds

SHF：小型：统一布局、器件仿真和过程仿真领域的高效且准确的方法

• 批准号: 1217076
• 负责人: Niraj Jha
• 金额: $ 45万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-07-01 至 2016-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1217076&HistoricalAwards=false
• 关键词: SHF; Small; Efficient; Accurate; Methodologies

Due to the severely degraded short-channel behavior of MOSFETs, Intel and TSMC have announced their switch to multi-gate FETs at the upcoming technology nodes. Hardware experiments with multi-gate devices and larger circuits entail very high cost and turnaround time. Thus, efficient predictive 3D-Technology CAD (3D-TCAD) based process/device characterization methods for such devices/circuits are urgently needed. A lack of such methods currently poses a significant impediment to rapid progress in this area. Though 3D-TCAD based exploration is essential for accurate predictive modeling, it is beset with major challenges which makes it necessary to develop a seamless set of methodologies/algorithms integrated with 3D-TCAD eco-systems for resolving process, layout, and device level issues quickly. The main aim of the proposed work is to develop efficient and accurate methodologies for unifying the layout, 2D/3D device simulation, and process simulation worlds, thereby, for the first time, expanding the horizon of predictive modeling for multi-gate devices beyond the many-device TCAD barrier, which is a major showstopper at lower technology nodes. The project aims to develop a set of versatile methodologies for synthesizing contiguous 2D/3D device-simulation-ready structures corresponding to given layouts, without the need for repetitive and expensive 3D process simulations on each layout. These methodologies are expected to yield several orders of magnitude speedup in TCAD structure generation for large layouts, with run-time reduction from days/weeks to a few hours per design and decreased memory footprints. The project will also develop fast cache-extrapolate-update techniques to alleviate the problem of obtaining convergence with iterative linear solvers for both mixed-mode and contiguous 3D device simulation.The methodologies developed in this research will break the many-device TCAD barrier and, by unifying layout with process/device simulation, make accurate and efficient predictive 3D-TCAD possible. The methodologies/tools that are developed will be disseminated through the web, conferences and journals. The material will be included in a course on Design with Nanotechnologies that the PI teaches at Princeton University. Princeton has a tradition of undergraduate independent research. Many senior students are expected to do their research project on this topic. Female and minority students will be attracted to this research through Princeton's Fellowship Program. Further outreach activities are also planned for high-school students.

由于 MOSFET 的短沟道行为严重退化，英特尔和台积电已宣布在即将到来的技术节点改用多栅极 FET。使用多门器件和更大电路的硬件实验需要非常高的成本和周转时间。因此，迫切需要针对此类器件/电路的基于高效预测 3D 技术 CAD (3D-TCAD) 的工艺/器件表征方法。目前缺乏此类方法对这一领域的快速进展构成了重大障碍。尽管基于 3D-TCAD 的探索对于准确的预测建模至关重要，但它面临着重大挑战，因此有必要开发一套与 3D-TCAD 生态系统集成的无缝方法/算法，以解决流程、布局和设备级问题迅速地。拟议工作的主要目的是开发高效、准确的方法来统一布局、2D/3D 器件仿真和工艺仿真世界，从而首次将多栅极器件的预测建模范围扩展到超出多设备 TCAD 障碍，这是较低技术节点的主要障碍。该项目旨在开发一套通用方法，用于合成与给定布局相对应的连续 2D/3D 器件模拟就绪结构，而无需对每个布局进行重复且昂贵的 3D 工艺模拟。这些方法预计将使大型布局的 TCAD 结构生成速度提高几个数量级，每个设计的运行时间从几天/几周减少到几个小时，并减少内存占用。该项目还将开发快速缓存外推更新技术，以缓解混合模式和连续 3D 设备仿真的迭代线性求解器获得收敛的问题。本研究开发的方法将打破多设备 TCAD 障碍，通过将布局与流程/设备仿真相统一，使准确、高效的预测性 3D-TCAD 成为可能。开发的方法/工具将通过网络、会议和期刊传播。该材料将包含在 PI 在普林斯顿大学教授的纳米技术设计课程中。普林斯顿大学有本科生独立研究的传统。许多高年级学生预计将开展有关该主题的研究项目。普林斯顿大学的奖学金计划将吸引女性和少数族裔学生参与这项研究。还计划为高中生开展进一步的外展活动。