SHF:Small: Fine-grain Dynamically Reconfigurable FPGA Architecture Aimed at Reducing the ASIC-FPGA Gaps

SHF:Small：旨在缩小 ASIC-FPGA 差距的细粒度动态可重构 FPGA 架构

• 批准号: 1216457
• 负责人: Niraj Jha
• 金额: $ 35万
• 依托单位: Princeton University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-09-01 至 2016-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1216457&HistoricalAwards=false
• 关键词: SHF; Small; Fine; grain; Dynamically

Field-programmable gate arrays (FPGAs) and application-specific integrated circuits (ASICs) are two very important processing elements for computation. FPGAs are very attractive because of their lower design cost and shorter time-to-market compared to ASICs. Still, the marketshare of FPGAs remains less than a fifth of that of ASICs because ASICs enjoy an advantage over FPGAs in terms of circuit area, power consumption, and delay. The objective of the proposed work is to significantly reduce these area/power/delay gaps through a new dynamically reconfigurable FPGA design and thus enable FPGAs to become much more competitive with ASICs. Continued scaling of bulk CMOS technology faces significant hurdles. To alleviate these problems, Intel and TSMC have already announced a switch to multi-gate field-effect transistors, e.g., Trigate and FinFETs, at the upcoming semiconductor technology nodes. Another important trend is towards 3D integrated circuits (ICs), in which multiple die layers are stacked on top of each other. 3D ICs promise a revolution in so called ``More than Moore" computing. The proposed work aims to take advantage of the multi-gate and 3D IC technologies to further reduce the gaps mentioned above.The proposed FPGA architecture significantly deviates from the conventional island-style FPGA architecture by enabling the logic element to either perform computation or local communication or both. It is aided by the key concept of temporal logic folding that allows a circuit to be drastically folded, aided by on-chip reconfiguration memory, before being mapped to the FPGA. It attacks the main reason for the area/power/delay gaps -- the vast amount of chip resources allocated to reconfigurable interconnects in FPGAs. Logic folding makes the communication local, thus making it possible to reduce the amount of resources devoted to interconnects very significantly. The work entails design space exploration of the different components of the architecture, investigation of novel multi-gate computation/communication structures, and algorithms and design automation tools to map arbitrary circuits to the FPGA architecture. It is expected to yield a well-characterized and highly versatile family of 3D multi-gate transistor based FPGAs that are competitive with ASICs. Work on various design methodologies and tools developed in this research will be disseminated through conference and journal articles. Technology transfer will be done through companies interested in using such FPGAs as accelerators. The material will be included in a senior-level course on Design with Nanotechnologies and a graduate-level course on Low Power IC and System Design introduced by the PI. Female and minority students will be attracted to this research through Princeton's Presidential Fellowship Program.

现场编程的门阵列（FPGA）和应用特定的集成电路（ASIC）是两个非常重要的处理元素的两个非常重要的处理元素。 FPGA非常有吸引力，因为与ASIC相比，其设计成本较低，而且市场上的时间较短。 尽管如此，FPGA的市场份额仍然不到ASIC的五分之一，因为ASIC在电路区域，功耗和延迟方面具有优于FPGA的优势。 拟议的工作的目的是通过新的可动力配置的FPGA设计大大减少这些区域/功率/延迟差距，从而使FPGA与ASIC变得更加竞争力。批量CMOS技术的持续扩展面临重大障碍。为了减轻这些问题，英特尔和TSMC已经宣布转向即将到来的半导体技术节点的多门现场效应晶体管，例如trigice和finfets。 另一个重要的趋势是朝着3D综合电路（IC）迈进，其中多个模具层彼此堆叠。 3D IC承诺在所谓的``超过摩尔''计算中都有一场革命。拟议的工作旨在利用多门和3D IC技术，进一步减少上述差距。拟议的FPGA体系结构显着偏离了传统的岛屿风格的FPGA，通过允许逻辑元素来允许一位逻辑型号，以允许一位逻辑型号来执行一项概念或构图。在映射到FPGA之前，请大幅度地折叠，并在芯片上进行重新配置。体系结构的组成部分，新型多门计算/通信结构的研究以及算法和设计自动化工具，以将任意电路映射到FPGA体系结构。预计它将产生与ASIC具有竞争力的3D多对晶体管FPGA的特征性和高度通用的家族。 这项研究中开发的各种设计方法和工具的工作将通过会议和期刊文章传播。 技术转移将通过有兴趣使用加速器等FPGA的公司进行。该材料将包括在具有纳米技术的高级设计课程中，以及PI引入的低功率IC和系统设计的研究生级课程。通过普林斯顿的总统奖学金计划，将吸引女学生和少数民族学生。