SHF: Small: Collaborative Research: Exploring Energy-Efficient GPGPUs Through Emerging Technology Integration

SHF：小型：协作研究：通过新兴技术集成探索节能 GPGPU

• 批准号: 1320100
• 负责人: Renato Figueiredo
• 金额: $ 24.37万
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-08-01 至 2018-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1320100&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Exploring

Nowadays, graphics processing units (GPUs) have been widely adopted for general-purpose computing, and are known as GPGPUs. However, current and future GPGPUs confront power and energy as the dominant constraints. The number of transistors integrated on a single GPU chip continues to increase due to shrinking feature size and the demand for massively parallel computing cores to increase throughput. On the other hand, the continuous decrease of transistor supply voltage at each new technology node has largely stalled because of leakage constraints, leading to an ever-increasing power density. Therefore, future GPGPUs must become more inherently energy efficient to avoid hitting the power wall. To meet the increasing demands on performance and energy-efficiency, emerging technologies such as non-volatile memory, inter-bank tunneling field effect transistors (TFETs), silicon nanophotonics, and three-dimensional (3D) integration are being deployed in hardware design and promise realization of power efficiency at a scale never expected before. The investigators are exploring a synergetic program to holistically and hierarchically improve the GPGPU's energy efficiency through emerging technology integration. The project objectives include (1) non-volatile memory in the GPU computing cores and low-power mechanisms to substantially reduce leakage and dynamic power consumption; (2) a hybrid TFET-CMOS (complementary metal-oxide semiconductor) methodology to effectively address the energy challenge at both intra- and inter-core levels; (3) a novel 3D-stacked throughput architecture based on silicon-nanophotonics technology to improve memory access performance yet reduce power consumption; (4) integration of the key research innovations and cross-technology optimizations to fully explore the potential of GPGPU design enabled by these emerging technologies. The proposed research will facilitate GPGPUs staying on track with deep sub-micron scaling and meeting the increasing demand for high-performance computing, and will hence benefit numerous real-life applications. This project will also contribute to society through engaging high-school and undergraduate students from minority-serving institutions in research, attracting women and other under-represented groups into graduate education, expanding the computer engineering curriculum with GPGPU power modeling and optimization techniques, disseminating research infrastructure for education and training, and collaborating with the GPU R&D industry.

如今，图形处理单元（GPU）已被广泛用于通用计算，被称为GPGPU。但是，当前和未来的GPGPU面临着权力和能量作为主要约束。由于特征大小的缩小以及对大量平行计算核心以增加吞吐量的需求，在单个GPU芯片上集成的晶体管数量继续增加。另一方面，由于泄漏的限制，每个新技术节点在每个新技术节点上的持续降低都大大停滞，从而导致功率密度不断增加。因此，未来的GPGPU必须变得更加固有地节能，以避免撞击电壁。为了满足对性能和能源效率的日益增长的需求，新兴技术（例如非挥发性记忆，银行间隧穿现场效应晶体管（TFET），硅纳米光子学和三维（3D）集成在硬件设计中已被部署在硬件设计中，并承诺在尺度上实现强力效率的实现。研究人员正在探索一项协同计划，以通过新兴技术整合从整体和分层提高GPGPU的能源效率。项目目标包括（1）GPU计算核心中的非易失性记忆和低功率机制，可大大降低泄漏和动态功耗； （2）一种混合TFET-CMO（互补的金属氧化物半导体）方法，可有效解决核内和核心间水平的能量挑战； （3）一种基于硅 - 纳米素技术技术的新颖的3D堆叠式体系结构，以改善内存访问性能，但降低功耗； （4）整合主要的研究创新和跨技术优化，以充分探索这些新兴技术实现的GPGPU设计的潜力。拟议的研究将促进GPGPU，以深度的亚微米缩放率保持正轨，并满足对高性能计算的需求不断增长的需求，因此将使众多现实生活中的应用受益。 This project will also contribute to society through engaging high-school and undergraduate students from minority-serving institutions in research, attracting women and other under-represented groups into graduate education, expanding the computer engineering curriculum with GPGPU power modeling and optimization techniques, disseminating research infrastructure for education and training, and collaborating with the GPU R&D industry.