Performance Driven Layout and Logic Synthesis

性能驱动布局和逻辑综合

• 批准号: 0098069
• 负责人: Malgorzata Marek-Sadowska
• 金额: $ 35.06万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-09-01 至 2005-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0098069&HistoricalAwards=false
• 关键词: Performance; Driven; Layout; Logic; Synthesis

The increased chip complexity causes that average interconnect lengths increase and proportionallylarger and larger fraction of chip's area is occupied by interconnects. This proposal addresses several is-suesrelated to interconnects in submicron technologies.We will concentrate on simultaneous switching cross-talk noise effects in RC interconnects. Our goalhere is to develop efficient, easy to compute and accurate bounds on delay in the presence of crosstalk andto characterize and prevent propagating crosstalk signals. Besides correcting the crosstalk caused prob-lemswe will also develop methodologies of circuit optimization in the presence of crosstalk. We will developgate sizing tool, buffer insertion, spacing and net reordering which will consider both cross-talk and delay.At the same time we will explore regularity at the Boolean level to achieve layouts with mostly localinterconnects. The ultimate goal is to develop logic synthesis methodology which would produce highly reg-ular layout structures without large area penalty. We propose to continue our work on wave steered design methodology and we will develop tools for logic synthesis and physical design of such circuits.

增加的芯片复杂性导致平均互连长度增加，而芯片面积的较大部分则被互连所占据。该提案涉及在亚微米技术中与互连相关的几个。我们将集中精力在RC互连中同时开关交叉噪声效应。我们的势头是在存在串扰和延迟的延迟方面发展有效，易于计算和准确的界限，以表征并防止传播串扰信号。除了纠正引起的串扰，在存在串扰的情况下还将开发出电路优化的方法论。我们将开发窗口尺寸的工具，缓冲区插入，间距和网络重新排序，这将考虑串扰和延迟。在同时我们将在布尔级探索规律性，以实现大多数LocalInterinternects的布局。最终目标是开发逻辑综合方法，该方法将产生高度较大的布局结构而不大面积惩罚。我们建议继续在Wave转向设计方法方面的工作，并将开发用于此类电路的逻辑合成和物理设计的工具。