Manufacturability-aware performance-driven layout-centric design automation of analog and RF integrated circuits

模拟和射频集成电路的可制造性感知、性能驱动、以布局为中心的设计自动化

• 批准号: 342185-2007
• 负责人: Zhang, Lihong
• 金额: $ 1.75万
• 依托单位: Memorial University of Newfoundland
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2007
• 资助国家: 加拿大
• 起止时间: 2007-01-01 至 2008-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=361317
• 关键词: Manufacturability; aware; performance; driven; layout

Analog/RF circuits have been recognized as the design bottleneck for getting System-on-Chip products to market due to the high sensitivity to the associated analog/RF effects and the limited availability of analog/RF computer-aided design (CAD) tools. In particular, so far most of analog/RF layouts have to be handcrafted by circuit designers. Thus, the layout-related constraints are hard to be satisfied and included in the circuit synthesis. In this proposal, the development of design methodology and CAD tools for robust circuit/layout synthesis of analog/RF integrated circuits in deep-submicron and nano technologies is proposed. This work will focus on setting up complete circuit synthesis flow, investigating performance-driven automatic layout generation, fully taking into account distinct manufacturability issues in the advanced technologies, and exploring layout automation aided by circuit tuning. This will be the first fully automated manufacturability- aware performance-driven layout-centric synthesis methodology for analog/RF integrated circuits. In the circuit synthesis flow, the layout automation is integrated. Circuit tuning takes into account the layout-related effects so that circuit topology and sizing can be refined. The proposed complete layout design flow is composed of automatic template generation and template-based compaction. We will develop a new template-based scheme based on the macro-cell layout approach to facilitate the intellectual property reuse. Thus, the generated layout is reliable in the sense of performance and manufacturability without compromising the design efficiency.        Having attracted strong interest in academia and industry, the circuit/layout design automation of analog/RF integrated circuits has enormous potential for commercialization. This proposed research work addresses the increasingly serious performance and manufacturability problems for analog/RF integrated circuits in deep-submicron and nano technologies. It will benefit analog/RF designers by significantly improving the design efficiency and reliability. This research program would enhance the competitive ability of Canada in this field.

由于对相关模拟/射频效应的高度敏感性以及模拟/射频计算机辅助设计 (CAD) 工具的可用性有限，模拟/射频电路已被认为是片上系统产品推向市场的设计瓶颈。特别是，到目前为止，大多数模拟/射频布局都必须由电路设计人员手工制作，因此，与布局相关的约束很难满足并包含在电路综合中，包括设计方法和 CAD 工具的开发。用于稳健的电路/布局综合提出了深亚微米和纳米技术中的模拟/射频集成电路，这项工作将侧重于建立完整的电路综合流程，研究性能驱动的自动布局生成，充分考虑先进技术中的独特可制造性问题，并探索布局。这将是第一个用于模拟/射频集成电路的完全自动化的、可制造性感知的、以性能驱动的布局为中心的综合方法。在电路综合流程中，布局自动化集成了布局。相关效应使得所提出的完整布局设计流程由自动模板生成和基于模板的压缩组成，我们将开发一种基于宏单元布局方法的新的基于模板的方案，以促进知识产权的重用。因此，生成的布局在性能和可制造性方面是可靠的，并且不影响设计效率，引起了学术界和工业界的浓厚兴趣，模拟/射频集成电路的电路/布局设计自动化具有巨大的潜力。这项拟议的研究工作解决了深亚微米和纳米技术中模拟/射频集成电路日益严重的性能和可制造性问题，它将通过显着提高设计效率和可靠性而使模拟/射频设计人员受益。加拿大在该领域的竞争能力。