Additive Patterning of Integrated Functional Materials on a Chip

芯片上集成功能材料的增材图案化

• 批准号: 0088206
• 负责人: Nancy Sottos
• 金额: $ 45万
• 依托单位: University of Illinois at Urbana-Champaign
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-09-15 至 2004-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0088206&HistoricalAwards=false
• 关键词: Additive; Patterning; Integrated; Functional; Materials

Nancy R. Sottos and David A. Payne, University of Illinois at Urbana-ChampaignProposal Number #0088206Additive Patterning of Integrated Functional Materials on a Chip A critical issue for the future engineering of microsystems on a chip is the ability to rapidly pattern dissimilar materials in complex integrated systems. A novel, additive method of patterning is proposed that will enable integration of functional materials (e.g., electrical, mechanical, optical, etc.) on a chip, rather than as a discrete component added into the circuit and system. Specifically, an interdisciplinary investigation is planned to examine additive patterning of integrated electroceramic thin film devices and to develop a better understanding of the complex residual stress development in the films during this process. Integration of electroceramic thin films is a key technology for the realization of future micro electromechanical (MEM) device applications such as miniaturized sensors and actuators, ultrasonic motors and optical elements as well as nonvolatile memory elements and switching capacitors for integrated circuitry. In order to advance this technology for the next generation of electromechanical devices, it is essential to develop a fundamental understanding of the residual stresses generated in the films during patterning, the effects of these stresses on film properties and how to tailor these stresses for optimal device performance. Specific goals of this interdisciplinary investigation include: (i) development of new protocols to pattern thicker electroceramic films and multilayer devices where residual stresses are most critical, (ii) in-situ measurement of residual stress development during patterning, (iii) development of analytical models to understand the role of the substrate, film adhesion, and processing conditions on residual stress, (iv) characterization of the electromechanical properties of patterned films and assess the effects of residual stress on performance, and (v) development of a strategy for tailoring the residual stress state for optimal performance and reliability of the device.

Nancy R. Sottos 和 David A. Payne，伊利诺伊大学厄巴纳-香槟分校提案号 #0088206 芯片上集成功能材料的增材图案化 芯片上微系统未来工程的一个关键问题是能够快速对复杂的不同材料进行图案化集成系统。 提出了一种新颖的附加图案化方法，该方法将能够将功能材料（例如电气、机械、光学等）集成在芯片上，而不是作为分立元件添加到电路和系统中。 具体来说，计划进行一项跨学科研究，以检查集成电陶瓷薄膜器件的加成图案，并更好地理解在此过程中薄膜中复杂的残余应力的发展。 电陶瓷薄膜的集成是实现未来微机电（MEM）器件应用的关键技术，例如微型传感器和执行器、超声波电机和光学元件以及集成电路的非易失性存储元件和开关电容器。 为了推进下一代机电设备的这项技术，必须对图案化过程中薄膜中产生的残余应力、这些应力对薄膜性能的影响以及如何调整这些应力以实现最佳设备有一个基本的了解表现。 这项跨学科研究的具体目标包括：(i) 开发新协议，以对较厚的电陶瓷薄膜和多层器件进行图案化，其中残余应力至关重要，(ii) 图案化过程中残余应力发展的原位测量，(iii) 开发分析方法模型以了解基材、薄膜粘附力和加工条件对残余应力的作用，(iv) 表征图案化薄膜的机电性能并评估残余应力对性能的影响，以及 (v) 制定定制策略最佳残余应力状态设备的性能和可靠性。