Digital Cancellation of Analog Mismatch Noise in Pipelined ADCs

流水线 ADC 中模拟失配噪声的数字消除

• 批准号: 0073552
• 负责人: Ian Galton
• 金额: $ 27.24万
• 依托单位: University of California-San Diego
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-09-01 至 2004-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0073552&HistoricalAwards=false
• 关键词: Digital; Cancellation; Analog; Mismatch; Noise

The purpose of this research is to extend the present performance limits of pipelined analog-to-digital converters (ADCs) through the development of a digital signal processing technique that corrects for analog circuit mismatches. With recent trends toward software reconfigurability and digital signal processing, pipelined ADCs have become widely used in applications such as cellular telephone base-stations and wideband wireline modems. However, analog component mismatches have limited the accuracy achieved by present fabricated pipelined ADCs to levels below those desirable in many communications applications. For example, the accuracy ceiling imposed by analog component mismatches in present pipelined ADCs with conversion rates at or above 10MHz is approximately 75dB peak signal-to-noise-and-distortion (SINAD). Several distinct mismatch calibration techniques have been proposed in recent years to address the mismatch problem, but so far they have not made it possible to break through the above-mentioned 75dB SINAD ceiling. The problem is that the calibration techniques proposed to date are ultimately limited by the precision of their analog components, which tends to decrease as the conversion rate is increased. This research involves the development of a new pipelined ADC mismatch calibration technique that avoids this problem. The new technique differs from other mismatch calibration schemes in that it continuously measures and cancels noise in the ADC output arising from component mismatches during normal operation of the ADC; no special calibration signals or auto-calibration phase are required prior to A/D conversion. Both the measurement and cancellation of mismatch noise are performed entirely using digital logic, but unlike previously proposed digital calibration techniques the technique does not require additional pipeline stages or bits per stage. The objectives of the research are to 1) refine the technique, 2) quantify its performance limits through simulation and theoretical analyses, and 3) develop a CMOS pipelined ADC prototype that achieves record-setting performance enabled by the technique as a proof-of-principle.

本研究的目的是通过开发纠正模拟电路不匹配的数字信号处理技术来扩展流水线模数转换器 (ADC) 目前的性能限制。 随着软件可重构性和数字信号处理的最新趋势，流水线 ADC 已广泛应用于蜂窝电话基站和宽带有线调制解调器等应用中。 然而，模拟元件失配将目前制造的流水线 ADC 所达到的精度限制在许多通信应用中低于所需水平的水平。 例如，当前转换速率等于或高于 10MHz 的流水线 ADC 中模拟组件不匹配所造成的精度上限约为 75dB 峰值信噪比和失真 (SINAD)。 近年来，人们提出了几种不同的失配校准技术来解决失配问题，但到目前为止，它们还没有能够突破上述75dB SINAD上限。 问题在于，迄今为止提出的校准技术最终受到其模拟组件精度的限制，随着转换率的提高，模拟组件的精度往往会降低。 这项研究涉及开发一种新的流水线 ADC 失配校准技术，可以避免这个问题。该新技术与其他失配校准方案的不同之处在于，它在 ADC 正常运行期间连续测量并消除因组件失配而产生的 ADC 输出中的噪声； A/D 转换之前不需要特殊的校准信号或自动校准阶段。 失配噪声的测量和消除完全使用数字逻辑来执行，但与之前提出的数字校准技术不同，该技术不需要额外的流水线级或每级的位数。该研究的目标是 1) 完善该技术，2) 通过仿真和理论分析量化其性能限制，以及 3) 开发 CMOS 流水线 ADC 原型，该原型可实现由该技术实现的创纪录性能，作为证明-原则。