CAREER: Design-For-Testability in Core-Based Designs

职业：基于核心的设计中的可测试性设计

• 批准号: 9702236
• 负责人: Nur Touba
• 金额: $ 22.85万
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 1997
• 资助国家: 美国
• 起止时间: 1997-09-01 至 2003-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9702236&HistoricalAwards=false
• 关键词: CAREER; Design; Testability; Core; Based

In order to shorten product development cycles for integrated circuits and systems, pre-designed cores are widely used as part of the on-chip logic. Testing core-based designs is a major issue because the internal design of the core may not be known if it is intellectual property. In that case standard manufacturing test strategies will not suffice. This research is exploring new methodologies for testing chips with embedded cores. The approach is to find methods for synthesizing the user-defined logic, in which cores reside, so that the whole design meets area, performance and test criteria. Synthesis algorithms are being developed which address the following concerns: 1. Application of test vectors to inputs of the core. 2. Observation of outputs from the user-defined logic that drive the inputs of the core. 3. Testing the user-defined logic driven by the outputs of the core. 4. Observation of outputs from the core.

为了缩短集成电路和系统的产品开发周期，预先设计的内核被广泛用作片上逻辑的一部分。测试基于内核的设计是一个主要问题，因为内核的内部设计可能不知道是否具有知识产权。在这种情况下，标准制造测试策略是不够的。这项研究正在探索测试嵌入式内核芯片的新方法。该方法是找到综合内核所在的用户定义逻辑的方法，以便整个设计满足面积、性能和测试标准。正在开发解决以下问题的综合算法： 1. 将测试向量应用于内核的输入。 2. 观察驱动内核输入的用户定义逻辑的输出。 3. 测试由内核输出驱动的用户定义逻辑。 4. 观察核心的输出。