SHF: Small: Efficient Test and Yield Enhancement Techniques for 3D Integrated Circuits

SHF：小型：3D 集成电路的高效测试和良率增强技术

• 批准号: 1217750
• 负责人: Nur Touba
• 金额: $ 36万
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-07-01 至 2016-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1217750&HistoricalAwards=false
• 关键词: SHF; Small; Efficient; Test; Yield

Three-dimensional integrated circuits (3D-ICs) using through-silicon vias (TSVs) is an important new technology that overcomes barriers in interconnect scaling. It provides significant advantages including increased functional density, higher performance, and lower power. This research project will explore new ideas, concepts, and directions for test and repair of 3D-ICs which hold promise to significantly reduce test costs and improve yield. The ability to select which dies/wafers are stacked together and in what order and with what rotational symmetry are degrees of freedom in constructing 3D-ICs that can be exploited. New strategies for using this to reduce the cost and increase the effectiveness of defect tolerance techniques will be investigated. To reduce test costs, new distributed test compression architectures will be developed which create a new paradigm for test scheduling enabling much greater flexibility and efficiency to shorten test time and improve product quality. This research project will generate new theory, concepts, and techniques for significantly improving test costs and yield for 3D-ICs. This is a key factor for keeping down the manufacturing costs of 3D chips and allowing them to penetrate new markets and benefit society. Knowledge and experience generated from this project will be incorporated into courses in VLSI design and test. Students will be trained and prepared for the next generation semiconductor workforce. Undergraduate students will be involved in the project, including those from underrepresented groups, through undergraduate research projects, senior design projects, and course projects based on this research.

使用硅通孔 (TSV) 的三维集成电路 (3D-IC) 是一项重要的新技术，可克服互连缩放方面的障碍。 它提供了显着的优势，包括增加的功能密度、更高的性能和更低的功耗。 该研究项目将探索 3D-IC 测试和修复的新想法、概念和方向，有望显着降低测试成本并提高产量。 选择将哪些芯片/晶圆堆叠在一起以及以何种顺序和何种旋转对称性堆叠在一起的能力是构建可利用的 3D-IC 的自由度。 将研究利用这一点来降低成本并提高缺陷容错技术有效性的新策略。 为了降低测试成本，将开发新的分布式测试压缩架构，为测试调度创建新的范例，从而实现更大的灵活性和效率，从而缩短测试时间并提高产品质量。该研究项目将产生新的理论、概念和技术，以显着提高 3D-IC 的测试成本和产量。 这是降低3D芯片制造成本并使其进入新市场并造福社会的关键因素。 该项目产生的知识和经验将纳入超大规模集成电路设计和测试课程中。 学生将为下一代半导体劳动力接受培训和准备。 本科生将通过本科研究项目、高级设计项目和基于本研究的课程项目参与该项目，包括来自代表性不足群体的学生。