面向TSV的时延故障检测及容错方法研究

Through-silicon via (TSV) has a high defect rate under the current TSV manufacturing and bonding processes, thereby seriously impacting the quality and yield of three-dimensional integrated circuits (3D ICs). To tackle this problem, this project will research delay fault detection and fault-tolerant design methods for TSV. The main contents to be researched are summarized as follows: (1) Ring oscillator based path delay measurement technique for TSV will be researched, which can be used to detect the delay fault of TSV; (2) Fault-tolerant design method for TSV based on the chain-like control technique will be researched, which can be used to repair defective TSVs and improve the yield of 3D ICs; (3) TSV selection and grouping method will be researched, which can be used to improve the effectiveness of TSV repair; (4) TSV expansion based critical path selection and delay testing method will be researched, which can be used to provide critical paths for TSV selection and grouping, and assure the timing correction of TSV after bonding and TSV repair; By TSV testing and repairing, the quality and yield of 3D ICs can be improved significantly, and the advantages of 3D ICs can be further realized at reduced costs.

TSV在制造和绑定过程中存在非常高的时延缺陷率，从而严重影响三维集成电路产品的品质和良率。针对这个问题，本项目拟计划研究面向TSV的时延故障检测以及容错设计方法，主要研究内容包括：(1)研究基于环形通路振荡的TSV传输时延测量方法，以此达到检测TSV时延故障的目的；(2)研究基于链式控制的缺陷TSV容错结构，以此实现缺陷TSV的容错并提升三维集成电路产品的良率；(3) 研究面向容错结构的TSV分组及选择方法，以此保障缺陷TSV的容错修复成功率；(4)研究基于TSV 扩展的关键通路选择和时延测试方法，为TSV分组和选择提供关键通路依据，并确保三维集成电路在绑定和容错修复后的时序正确性。通过研究面向TSV的时延故障检测和容错设计方法，可以显著提升三维集成电路产品的品质和良率，并以此降低三维集成电路产品的成本。

三维集成电路中的TSV易于在绑定前和绑定过程中产生缺陷，从而严重影响三维集成电路产品的品质和良率。针对这个问题，本项目主要开展了面向TSV的时延故障检测以及容错设计方法，关注了三维集成电路绑定前和三维集成电路绑定后缺陷检测及容错方法，重点研究成果包括: 1）在三维集成电路芯片绑定前，依据TSV存在缺陷的情况下将对其电阻电容参数产生影响，并进一步导致环形振荡周期发生变化，实现TSV缺陷的检测与容错；2）在三维集成电路芯片绑定后，利用高速片上环形振荡技术实现对TSV传输时延测量，获取TSV的实际传输时延值，从而达到对TSV上的缺陷进行有效检测及容错的目的。通过研究面向TSV的时延故障检测和容错设计方法，可以显著提升三维集成电路产品的品质和良率。

内容获取失败，请点击重试