Analog Integrated Circuits in Nano-scale Emerging Technologies

纳米级新兴技术中的模拟集成电路

• 批准号: RGPIN-2016-05681
• 负责人: ElMasry, Ezz
• 金额: $ 2.26万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2022
• 资助国家: 加拿大
• 起止时间: 2022-01-01 至 2023-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=751583
• 关键词: Analog; Integrated; Circuits; Nano; scale; Analog; Integrated; Circuits; Nano; scale

The classical planar CMOS transistor is reaching its scaling limits and “end-of-roadmap”. This has been concluded as a result of the following shortcomings of nano-scale planar MOSFETs: undesirable process variations, short channel effects, high drain induced barrier lowering, substantial leakage currents, lower intrinsic gain, lower output impedance, lower dynamic range, poorer device matching and threshold voltage fluctuations. These non-idealities eventually degrade the performance of CMOS devices and pose a serious threat to nano-scale integrated circuits performance. Therefore, robust RF, analog and mixed-signal circuits using nano-scale bulk CMOS devices beyond the 32-nm node may no longer be practical. Alternative devices that have been investigated are the FinFETs. These devices are suitable candidates to replace planar MOSFETs in technology below 32-nm node. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and calls them “Advanced non-classical CMOS devices”. While the advantages of the FinFETs started to reap its fruit for digital circuits, adopting FinFETs for analog circuits leave the analog designer with new challenges and problems to tackle. Therefore, new specialized circuits design techniques and new architectures need to be developed. This provides the motivation for this research project. We will explore the use of FinFETs to develop high performance, low-voltage and low-power analog and mixed-signal integrated circuits design techniques for future nano-scale systems implementation. Achieving the proposed objectives would advance the analog circuit designer knowledge. The principal beneficiaries of this work will be researchers and designers working on System-on-Chip solutions for telecommunication, biomedical and sensor applications. Where the need for low-cost, wearable/implantable monitoring devices using indirect measurement techniques becomes extremely useful in both monitoring and possibly keeping health costs down. Moreover, this research work has the potential to provide valuable intellectual property that can be used to develop useful applications for the scientific and industrial markets. Finally, the proposed research project represents a remarkable capacity to innovate; hence, it will be the subject for several prestigious journals, international conferences publications and possibly patents.

经典的平面CMOS晶体管达到了缩放限制和“公路结束图”。由于纳米级平面MOSFET的以下缺点：不良过程变化，短通道效应，高排水诱导的屏障降低，大量泄漏电流，较低的固有增益，较低的输出障碍，较低的动态范围，较低的动态范围，设备较差和设备匹配较差和阈值电量波动。这些非理想性最终降低了CMOS设备的性能，并对纳米级集成电路的性能构成了严重威胁。因此，使用纳米级散装CMOS设备以外的32 nm节点以外的纳米级散装CMOS设备的强大RF，模拟和混合信号回路可能不再是实用的。已经调查的替代设备是FinFets。这些设备是替代32 nm节点以下技术的平面MOSFET的合适候选者。半导体的国际技术路线图（ITRS）认识到这些设备的重要性，并称其为“先进的非经典CMOS设备”。虽然FinFets的优势开始从数字电路中收获果实，但采用FinFET用于模拟电路，使模拟设计师面临着新的挑战和问题。因此，需要开发新的专业电路设计技术和新的架构。这为该研究项目提供了动力。我们将探索使用FinFET来开发高性能，低压和低功率模拟和混合信号集成电路设计技术，以实现未来的纳米级系统实现。实现提出的目标将推进模拟电路设计师知识。这项工作的主要苯甲部将是从事用于电信，生物医学和传感器应用的芯片解决方案的研究人员和设计师。在使用间接测量技术的低成本，可穿戴/可植入的监视设备的需求中，在监视和可能保持健康成本的情况下非常有用。此外，这项研究工作有可能提供有价值的知识产权，可用于为科学和工业市场开发有用的应用。最后，拟议的研究项目代表了出色的创新能力。因此，这将是几个著名期刊，国际会议出版物和可能的专利的主题。