Analog Integrated Circuits in Nano-scale Emerging Technologies

纳米级新兴技术中的模拟集成电路

• 批准号: RGPIN-2016-05681
• 负责人: ElMasry, Ezz
• 金额: $ 2.26万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2022
• 资助国家: 加拿大
• 起止时间: 2022-01-01 至 2023-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=751583
• 关键词: Analog; Integrated; Circuits; Nano; scale

The classical planar CMOS transistor is reaching its scaling limits and “end-of-roadmap”. This has been concluded as a result of the following shortcomings of nano-scale planar MOSFETs: undesirable process variations, short channel effects, high drain induced barrier lowering, substantial leakage currents, lower intrinsic gain, lower output impedance, lower dynamic range, poorer device matching and threshold voltage fluctuations. These non-idealities eventually degrade the performance of CMOS devices and pose a serious threat to nano-scale integrated circuits performance. Therefore, robust RF, analog and mixed-signal circuits using nano-scale bulk CMOS devices beyond the 32-nm node may no longer be practical. Alternative devices that have been investigated are the FinFETs. These devices are suitable candidates to replace planar MOSFETs in technology below 32-nm node. The International Technology Roadmap for Semiconductors (ITRS) recognizes the importance of these devices and calls them “Advanced non-classical CMOS devices”. While the advantages of the FinFETs started to reap its fruit for digital circuits, adopting FinFETs for analog circuits leave the analog designer with new challenges and problems to tackle. Therefore, new specialized circuits design techniques and new architectures need to be developed. This provides the motivation for this research project. We will explore the use of FinFETs to develop high performance, low-voltage and low-power analog and mixed-signal integrated circuits design techniques for future nano-scale systems implementation. Achieving the proposed objectives would advance the analog circuit designer knowledge. The principal beneficiaries of this work will be researchers and designers working on System-on-Chip solutions for telecommunication, biomedical and sensor applications. Where the need for low-cost, wearable/implantable monitoring devices using indirect measurement techniques becomes extremely useful in both monitoring and possibly keeping health costs down. Moreover, this research work has the potential to provide valuable intellectual property that can be used to develop useful applications for the scientific and industrial markets. Finally, the proposed research project represents a remarkable capacity to innovate; hence, it will be the subject for several prestigious journals, international conferences publications and possibly patents.

经典平面 CMOS 晶体管已达到其尺寸极限，并且“路线图已结束”，这是由于纳米级平面 MOSFET 存在以下缺点：不良工艺变化、短沟道效应、高漏极感应势垒降低。 、大量的漏电流、较低的固有增益、较低的输出阻抗、较低的动态范围、较差的器件匹配和阈值电压波动，这些非理想因素最终会降低 CMOS 器件的性能，并对纳米级器件构成严重威胁。因此，使用超过 32 nm 节点的纳米级体 CMOS 器件的稳健 RF、模拟和混合信号电路可能不再适用，FinFET 是已研究的替代器件。取代 32 nm 节点以下技术中的平面 MOSFET。国际半导体技术路线图 (ITRS) 认识到这些器件的重要性，并将其称为“先进的非经典 CMOS”。虽然 FinFET 的优势开始在数字电路中体现出来，但在模拟电路中采用 FinFET 却给模拟设计人员带来了新的挑战和问题需要解决，因此需要开发新的专用电路设计技术和新的架构。我们将探索使用 FinFET 开发高性能、低电压和低功耗模拟和混合信号集成电路设计技术，以实现未来的纳米级实现系统。这项工作的主要受益者将是致力于电信、生物医学和传感器应用的片上系统解决方案的研究人员和设计人员，这些领域需要低成本、可穿戴/植入式监控设备。间接测量技术在监测和可能降低健康成本方面变得非常有用。此外，这项研究工作有可能提供宝贵的知识产权，可用于为科学和工业市场开发有用的应用。因此，它代表着卓越的创新能力；将成为一些著名期刊、国际会议出版物以及可能的专利的主题。