Low-voltage and low-power analog integrated circuits

低压低功耗模拟集成电路

• 批准号: 5965-2006
• 负责人: ElMasry, Ezz
• 金额: $ 2.33万
• 依托单位: Dalhousie University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2006
• 资助国家: 加拿大
• 起止时间: 2006-01-01 至 2007-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=338863
• 关键词: Low; voltage; low; power; analog

Analog integrated circuits (IC's) designers have been forced, primarily by economics, to develop circuits using the dominant digital Complementary Metal Oxide Semiconductor (CMOS) technologies. In CMOS the supply voltage continues to scale down and it is expected (in only couple of years) to be as low as 0.7 V in 70 nm CMOS technologies. Even if the process technology didn't require reduce supply voltages, the rapidly growing reliance on battery-powered microsystems (such as portable consumer electronics, computing devices, wireless communication systems, and biomedical implants) has led to an increase need for high performance ICs that operate under low supply voltage, consume low-power (LV/LP) and capable of high frequency operation. On top of this continuous drive for performance improvement, there is also the continuing march of Moor's Law, which drives future microsystems to be implemented in nanometer CMOS process. High performance analog circuits become increasingly difficult to implement in deep sub-micron CMOS due to the reduced intrinsic small signal gain and device headroom, making previously acceptable analog topologies and technologies obsolete. Therefore, new specialized design techniques, new topologies and new architectures are needed. This provides the motivation for this research project. It explores LV and LP analog IC's design techniques and develops new high performance analog devices for future microsystems implementations.

模拟综合电路（IC）设计师主要是由经济学强迫使用优势数字互补金属氧化物半导体（CMOS）技术来开发电路的。在CMO中，供应电压继续降低，预计（仅在几年内）在70 nm CMOS技术中将低至0.7 V。即使过程技术不需要降低供应电压，对电池供电的微型系统的迅速依赖（例如便携式消费电子，计算设备，无线通信系统和生物医学植入物）也导致了对高性能IC的需求在低电源电压下运行，消耗低功率（LV/LP），并且能够进行高频操作。除了这种不断提高性能的驱动力之外，还有摩尔定律的持续游行，该法律驱动了未来的微型系统将在纳米CMOS过程中实施。由于固有的小信号增益和设备头部空间的减少，高性能模拟电路在深层微米CMOS中变得越来越难以实施，因此使以前可接受的模拟拓扑结构和技术过时。因此，需要新的专业设计技术，新的拓扑和新的架构。这为该研究项目提供了动力。它探索了LV和LP Analog IC的设计技术，并为未来的Microsystems实现开发了新的高性能模拟设备。