Next-Generation Computer Aided Design Flow Challenges for Field Programmable Gate Arrays

现场可编程门阵列的下一代计算机辅助设计流程挑战

• 批准号: 341516-2012
• 负责人: Shannon, Lesley
• 金额: $ 1.31万
• 依托单位: Simon Fraser University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2019
• 资助国家: 加拿大
• 起止时间: 2019-01-01 至 2020-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=676913
• 关键词: Next; Generation; Computer; Aided; Design

Field Programmable Gate Arrays (FPGAs) are an alternative to custom chip design; they can be configured, in the field, to implement any circuit. Modern FPGAs contain a reconfigurable array of Configurable Logic Blocks (CLBs), embedded hard Intellectual Property (IP) blocks, and a programmable routing fabric and have one of the highest transistor counts per device. They use the same leading-edge process technology that is otherwise only used by computer processor companies (e.g. Intel, NVIDIA). The latest devices from Altera and Xilinx are fabricated with 28nm process technology with transistor counts of 3.9 and 6.8 billion, respectively. For many companies, FPGAs provide sufficient capacity and speed, allowing the company go "fabless" to avoid the expensive and time consuming services of a foundry. A Computer Aided Design (CAD) flow is used to transform an HDL description of a circuit into a programming bit stream. In this flow, the HDL is first synthesized into a Register-Transfer-Level (RTL) description of the circuit, which is technology mapped and clustered into the specific logic components on that device. The placement phase assigns specific locations on the device to these components and the routing phase determines an appropriate configuration of the routing fabric to provide the needed connectivity between components. FPGA CAD algorithms typically optimize for performance, area, and more recently power. However, today this is not enough. This research will provide advances in CAD algorithms in two areas. First, as process technology sizes decrease, issues such as process variation, and more recently device deterioration reducing the life time of chips, are increasing concerns. The first part of this research will address CAD flows that optimize for FPGA longevity. Research has also demonstrated that the processing power of computing workstations has failed to keep pace with the increasing complexity of FPGA designs, creating a productivity gap of 11x. The second part of the research will focus on reducing this gap through parallelization.

现场可编程栅极阵列（FPGA）是自定义芯片设计的替代方法；可以在现场配置它们以实现任何电路。现代FPGA包含可配置的可配置逻辑块（CLB），嵌入式硬知识属性（IP）块和可编程路由结构的可重新配置阵列，并具有每个设备最高的晶体管计数之一。他们使用相同的前沿过程技术，否则仅由计算机处理器公司（例如Intel，Nvidia）使用。来自Altera和Xilinx的最新设备由28NM工艺技术制造，晶体管计数分别为3.9亿和68亿。对于许多公司而言，FPGA提供足够的容量和速度，使公司“ Fables”避免了铸造厂的昂贵且耗时的服务。 计算机辅助设计（CAD）流用于将电路的HDL描述转换为编程位流。在此流中，首先将HDL合成为电路的寄存器 - 转移级别（RTL）描述，该描述是技术映射并聚集到该设备上的特定逻辑组件中。放置阶段将设备上的特定位置分配给这些组件，路由阶段决定了路由结构的适当配置，以提供组件之间所需的连接。 FPGA CAD算法通常针对性能，区域和最近的功率进行优化。但是，今天这还不够。这项研究将在两个领域提供CAD算法的进步。首先，随着过程技术的尺寸减少，诸如过程变化之类的问题以及最近减少芯片寿命的设备劣化的问题正在越来越令人担忧。这项研究的第一部分将解决为FPGA寿命优化的CAD流。研究还表明，计算工作站的处理能力未能跟上FPGA设计的复杂性的步伐，从而创造了11倍的生产力差距。研究的第二部分将集中于通过并行化来减少这一差距。