Next-Generation Computer Aided Design Flow Challenges for Field Programmable Gate Arrays

现场可编程门阵列的下一代计算机辅助设计流程挑战

• 批准号: 341516-2012
• 负责人: Shannon, Lesley
• 金额: $ 1.31万
• 依托单位: Simon Fraser University
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2019
• 资助国家: 加拿大
• 起止时间: 2019-01-01 至 2020-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=676913
• 关键词: Next; Generation; Computer; Aided; Design

Field Programmable Gate Arrays (FPGAs) are an alternative to custom chip design; they can be configured, in the field, to implement any circuit. Modern FPGAs contain a reconfigurable array of Configurable Logic Blocks (CLBs), embedded hard Intellectual Property (IP) blocks, and a programmable routing fabric and have one of the highest transistor counts per device. They use the same leading-edge process technology that is otherwise only used by computer processor companies (e.g. Intel, NVIDIA). The latest devices from Altera and Xilinx are fabricated with 28nm process technology with transistor counts of 3.9 and 6.8 billion, respectively. For many companies, FPGAs provide sufficient capacity and speed, allowing the company go "fabless" to avoid the expensive and time consuming services of a foundry. A Computer Aided Design (CAD) flow is used to transform an HDL description of a circuit into a programming bit stream. In this flow, the HDL is first synthesized into a Register-Transfer-Level (RTL) description of the circuit, which is technology mapped and clustered into the specific logic components on that device. The placement phase assigns specific locations on the device to these components and the routing phase determines an appropriate configuration of the routing fabric to provide the needed connectivity between components. FPGA CAD algorithms typically optimize for performance, area, and more recently power. However, today this is not enough. This research will provide advances in CAD algorithms in two areas. First, as process technology sizes decrease, issues such as process variation, and more recently device deterioration reducing the life time of chips, are increasing concerns. The first part of this research will address CAD flows that optimize for FPGA longevity. Research has also demonstrated that the processing power of computing workstations has failed to keep pace with the increasing complexity of FPGA designs, creating a productivity gap of 11x. The second part of the research will focus on reducing this gap through parallelization.

现场可编程门阵列 (FPGA) 是定制芯片设计的替代方案；它们可以在现场进行配置以实现任何电路。现代 FPGA 包含可重新配置的可配置逻辑块 (CLB) 阵列、嵌入式硬知识产权 (IP) 块和可编程路由结构，并且是每个器件中晶体管数量最多的器件之一。它们使用相同的前沿处理技术，而这些技术仅由计算机处理器公司（例如英特尔、NVIDIA）使用。 Altera 和 Xilinx 的最新器件采用 28nm 工艺技术制造，晶体管数量分别为 3.9 和 68 亿。对于许多公司来说，FPGA 提供了足够的容量和速度，使公司能够“无晶圆厂”，以避免代工厂昂贵且耗时的服务。 计算机辅助设计 (CAD) 流程用于将电路的 HDL 描述转换为编程位流。在此流程中，HDL 首先被合成为电路的寄存器传输级 (RTL) 描述，该描述经过技术映射并聚集到该设备上的特定逻辑组件中。布局阶段将设备上的特定位置分配给这些组件，而路由阶段确定路由结构的适当配置，以提供组件之间所需的连接。 FPGA CAD 算法通常针对性能、面积以及最近的功耗进行优化。然而，今天这还不够。这项研究将在两个领域推动 CAD 算法的进步。首先，随着工艺技术尺寸的减小，工艺变化以及最近导致芯片寿命缩短的器件退化等问题越来越受到关注。本研究的第一部分将解决针对 FPGA 寿命进行优化的 CAD 流程。研究还表明，计算工作站的处理能力无法跟上 FPGA 设计日益复杂的步伐，从而造成 11 倍的生产力差距。研究的第二部分将侧重于通过并行化来缩小这一差距。