Design and VLSI implementations of DSP algorithms for communication systems

通信系统 DSP 算法的设计和 VLSI 实现

• 批准号: 288185-2006
• 负责人: AbdelRaheem, Esam
• 金额: $ 0.87万
• 依托单位: University of Windsor
• 依托单位国家: 加拿大
• 项目类别: Discovery Grants Program - Individual
• 财政年份: 2006
• 资助国家: 加拿大
• 起止时间: 2006-01-01 至 2007-12-31
• 项目状态: 已结题
• 来源: https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=338944
• 关键词: Design; VLSI; implementations; DSP; algorithms

The proposed research will leverage the invistigation of innovative solutions in the design and VLSI implementations of digital signal processing (DSP) algorithms for communication systems. Solutions that would lead to high performance, low complexity and low-power consumptions will be adopted. Objectives of the project are: (1) To further develop blind equalization techniques that have shorter time-to-convergence (TTC) quality to suit high-speed communication systems and for other  modulation schemes implemented in wireless communication standards (i.e., DPSK, DQPSK, GMSK, etc.). (2) To further develop computationally-efficient blind adaptive equalization techniques that reduce both the amount of computations and hence increase the system's throughput, and/or decrease hardware complexity. (3)To develop programmable/reconfigurable blind adaptive equalizer so that their filter lengths, adaptation parameters, and error measure are variables according to the modulation utilized in the receiver for multi-standard future communication equipments (also as in software-defined radios). (4) To develop low-lardware-complexity and/or computationally-efficient adaptive algorithms for echo cancellation applications in communication systems. (5)To achieve low-power in blind adaptive equalizers and adaptive echo cancellers (AECs) to respond to the increased demand of fast-growing mobile communication services. (6)To develop VLSI implementations of blind adaptive equalizers and echo cancellers that incorporate both high-speed, low-power, and low-complexity requirements. (7) To achieve performance enhancement and robustness of 802.11a/RA for high vehicular velocity, so that higher data rates may be achieved in a 5.9GHz Dedicated Short Range Communication (DSRC) system.   (8)To confirm feasibility, consider the complexity of the receiver design, and maintain consistency with the 802.11a/RA standard.

拟议的研究将利用创新解决方案在数字信号处理（DSP）算法的设计和VLSI实现中的不受欢迎。将采用导致高性能，低复杂性和低功率消耗的解决方案。该项目的目标是：（1）进一步开发具有较短时间连接时间（TTC）质量的盲人均衡技术，以适合高速通信系统以及针对无线通信标准实施的其他调制方案（即DPSK，DQPSK，GMSK等）。 （2）进一步开发计算高效的盲目自适应均衡技术，以减少计算量并因此增加了系统的吞吐量和/或降低硬件复杂性。 （3）开发可编程/可重新配置的盲目自适应均衡器，以使其过滤器的长度，适应参数和误差测量是根据接收器中使用的调制，用于多标准的将来的通信设备（也是软件定义的无线电）。 （4）为通信系统中的回声取消应用程序开发低速器软件和/或计算效率的自适应算法。 （5）在盲目自适应均衡器和自适应回声取消器（AEC）中实现低功率，以应对快速增长的移动通信服务的需求增加。 （6）开发VLSI的实现，对盲目的自适应均衡器和回声取消器，这些取消器均包含高速，低功率和低复杂性要求。 （7）为了实现802.11a/ra的性能提高和鲁棒性，以达到高速车速，以便在5.9GHz专用的短距离通信（DSRC）系统中可以实现更高的数据速率。 （8）确认可行性，请考虑接收器设计的复杂性，并与802.11A/RA标准保持一致性。