Design and VLSI implementations of DSP algorithms for communication systems

通信系统 DSP 算法的设计和 VLSI 实现

基本信息

批准号：
288185-2006
负责人：
AbdelRaheem, Esam
金额：
$ 0.87万
依托单位：
University of Windsor
依托单位国家：
加拿大
项目类别：
Discovery Grants Program - Individual
财政年份：
2007
资助国家：
加拿大
起止时间：
2007-01-01 至 2008-12-31
项目状态：
已结题

来源：
https://www.nserc-crsng.gc.ca/ase-oro/Details-Detailles_eng.asp?id=365523
关键词：
Design VLSI implementations DSP algorithms

项目摘要

The proposed research will leverage the invistigation of innovative solutions in the design and VLSI implementations of digital signal processing (DSP) algorithms for communication systems. Solutions that would lead to high performance, low complexity and low-power consumptions will be adopted. Objectives of the project are: (1) To further develop blind equalization techniques that have shorter time-to-convergence (TTC) quality to suit high-speed communication systems and for other modulation schemes implemented in wireless communication standards (i.e., DPSK, DQPSK, GMSK, etc.). (2) To further develop computationally-efficient blind adaptive equalization techniques that reduce both the amount of computations and hence increase the system's throughput, and/or decrease hardware complexity. (3)To develop programmable/reconfigurable blind adaptive equalizer so that their filter lengths, adaptation parameters, and error measure are variables according to the modulation utilized in the receiver for multi-standard future communication equipments (also as in software-defined radios). (4) To develop low-lardware-complexity and/or computationally-efficient adaptive algorithms for echo cancellation applications in communication systems. (5)To achieve low-power in blind adaptive equalizers and adaptive echo cancellers (AECs) to respond to the increased demand of fast-growing mobile communication services. (6)To develop VLSI implementations of blind adaptive equalizers and echo cancellers that incorporate both high-speed, low-power, and low-complexity requirements. (7) To achieve performance enhancement and robustness of 802.11a/RA for high vehicular velocity, so that higher data rates may be achieved in a 5.9GHz Dedicated Short Range Communication (DSRC) system. (8)To confirm feasibility, consider the complexity of the receiver design, and maintain consistency with the 802.11a/RA standard.

拟议的研究将利用通信系统数字信号处理 (DSP) 算法的设计和 VLSI 实现中的创新解决方案，从而实现高性能、低复杂性和低功耗的解决方案。项目包括：(1) 进一步开发具有较短收敛时间 (TTC) 质量的盲均衡技术，以适应高速通信系统和无线通信标准中实施的其他调制方案（即，（DPSK、DQPSK、GMSK 等） (2) 开发进一步计算高效的盲自适应均衡技术，以减少计算量，从而增加系统的吞吐量，和/或降低硬件复杂性。可编程/可重配置盲自适应均衡器，以便它们的滤波器长度、自适应参数和误差测量根据多标准未来通信设备（也如软件定义无线电）的接收器中使用的调制而变化。 (4) 为通信系统中的回声消除应用开发低硬件复杂性和/或计算高效的自适应算法。 (5) 实现盲自适应均衡器和自适应回声消除器 (AEC) 的低功耗，以响应增加的信号。 (6) 开发盲自适应均衡器和回声消除器的 VLSI 实现，同时满足高速、低功耗和低复杂性要求。 (7) 实现性能增强和增强。 802.11a/RA 对高车速的鲁棒性，以便在 5.9GHz 专用短程通信 (DSRC) 系统中实现更高的数据速率 (8) 为了确认可行性，请考虑接收器设计的复杂性并保持一致性。符合 802.11a/RA 标准。