A new low-complexity paradigm for analogue computation and hardware learning

用于模拟计算和硬件学习的新的低复杂度范式

基本信息

  • 批准号:
    EP/V002759/1
  • 负责人:
  • 金额:
    $ 142.79万
  • 依托单位:
  • 依托单位国家:
    英国
  • 项目类别:
    Fellowship
  • 财政年份:
    2021
  • 资助国家:
    英国
  • 起止时间:
    2021 至 无数据
  • 项目状态:
    未结题

项目摘要

The Fellow and his team are seeking to develop a ground-breaking electronic device named the multimodal transistor. Arising from more than a decade of experience in unconventional device design, it allows for entirely new applications such as hardware learning, analog computation and control, while being energy efficient and easy to fabricate.News headlines in electronic devices usually hail developments in nanoscale billion-transistor chips, yet there are major opportunities for innovation in display screen technologies, in which the requirement of fabricating circuits at low cost over large areas, and not ultimate miniaturization, is prevalent. Existing fabrication facilities are now partly being repurposed for emerging large area electronic (LAE) applications: microfluidics, lab-on-a chip, ubiquitous sensors or wearable electronics. LAE usually contain large arrays of relatively simple circuits with few transistors, as areal performance variations impede the fabrication of complex circuits. Incremental progress in LAE is constantly achieved through processes and equipment improvements, and by using new materials with superior properties, both with large capital investment. The Fellow proposes a major step in LAE development, a radical new device design: the multimodal transistor (MMT). The MMT enables new ways of designing electronic circuits for efficient analog operations (amplification, data conversion, analog computation), control and feedback, and ultimately, LAE circuits capable of learning (hardware AI), so far impractical with conventional devices and techniques. Functionality is achieved using energy-efficient circuits of minimal complexity, allowing environmentally friendly fabrication at low cost. By greatly expanding the design possibilities, while being entirely compatible with conventional LAE fabrication, MMT circuits extend the usable lifetime of current manufacturing technologies, maximising the return on investment, and can accelerate the uptake of emerging processes such as 2D semiconductors and spatial atomic layer deposition.The Fellow's team will leverage our long experience in device design and the complementary capabilities of our international partners to design, fabricate and test devices and circuits using vacuum processing and additive manufacturing in conventional and emergent semiconductor systems, supported by state-of-the-art numerical simulation. The team will use their extensive collaborator networks to seed the development of a new electronic design paradigm.As this is an enabling technology, its applications span fields from disposable medical diagnostics and crop monitoring to autonomous vehicle control, new forms user interfaces and immersive entertainment environments, with substantial long term economical and public benefits for the UK and the world. The implications of the novel functionality, such as hardware AI and autonomy, will be a constantly considered. Stakeholders will be involved in shaping the research through cross-disciplinary workshops, online engagement and science festival participation. The focus on people will further include: continuing a decade-long tradition of training, mentoring and involving school students in the Fellow's research; supporting a strong start to the careers of young researchers involved through mentoring, independence and due to the ground-breaking nature of the work; and incorporating the findings into Surrey's teaching curriculum to increase our graduates' employability. The Fellowship will accelerate the Fellow's growth as an international technical and thought leader, while retaining valuable skills, intellectual property and know-how in the UK at a time of global uncertainty. A Fellowship is the optimal funding route, allowing full commitment to advancing this trailblazing design paradigm, within a robust structure and collaborative environment which includes world-leading research facilities and support networks.
该研究员和他的团队正在寻求开发一种名为多模晶体管的突破性电子设备。它源于十多年非常规设备设计的经验,它允许全新的应用,例如硬件学习、模拟计算和控制,同时具有高能效且易于制造。电子设备的新闻头条通常会欢呼纳米级数十亿美元的发展。晶体管芯片,但显示屏技术存在重大创新机会,其中普遍要求以低成本大面积制造电路,而不是最终小型化。现有的制造设施现在部分被重新用于新兴的大面积电子 (LAE) 应用:微流体、芯片实验室、无处不在的传感器或可穿戴电子产品。 LAE 通常包含大量相对简单的电路和很少的晶体管,因为面积性能变化阻碍了复杂电路的制造。 LAE 的不断进步是通过工艺和设备改进以及使用性能优越的新材料不断实现的,两者都需要大量的资本投资。该研究员提出了 LAE 开发的一个重要步骤,即一种全新的器件设计:多模晶体管 (MMT)。 MMT 实现了设计电子电路的新方法,以实现高效的模拟操作(放大、数据转换、模拟计算)、控制和反馈,并最终实现具有学习能力的 LAE 电路(硬件 AI),而迄今为止,传统设备和技术尚不切实际。功能是通过使用复杂性最小的节能电路来实现的,从而可以以低成本进行环保制造。通过极大扩展设计可能性,同时与传统 LAE 制造完全兼容,MMT 电路延长了当前制造技术的使用寿命,最大限度地提高了投资回报,并可以加速新兴工艺(例如 2D 半导体和空间原子层沉积)的采用该研究员的团队将利用我们在器件设计方面的长期经验以及我们国际合作伙伴的互补能力,在传统和新兴半导体系统中使用真空处理和增材制造来设计、制造和测试器件和电路,并得到最先进的支持艺术数值模拟。该团队将利用其广泛的合作者网络来开发新的电子设计范例。由于这是一项使能技术,其应用涵盖从一次性医疗诊断和农作物监测到自动驾驶车辆控制、新形式用户界面和沉浸式娱乐环境等领域,为英国和世界带来巨大的长期经济和公共利益。硬件人工智能和自主性等新颖功能的影响将不断得到考虑。利益相关者将通过跨学科研讨会、在线参与和科学节参与塑造研究。对人的关注将进一步包括:延续长达十年的培训、指导和让学生参与研究员研究的传统;通过指导、独立性以及工作的开创性,支持年轻研究人员的职业生涯有一个良好的开端;并将研究结果纳入萨里的教学课程中,以提高毕业生的就业能力。该奖学金将加速该研究员作为国际技术和思想领袖的成长,同时在全球不确定的时期在英国保留宝贵的技能、知识产权和专业知识。奖学金是最佳的资助途径,允许在强大的结构和协作环境(包括世界领先的研究设施和支持网络)内全面致力于推进这一开创性的设计范例。

项目成果

期刊论文数量(10)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Extraordinarily Weak Temperature Dependence of the Drain Current in Small-Molecule Schottky-Contact-Controlled Transistors through Active-Layer and Contact Interplay
通过有源层和接触相互作用,小分子肖特基接触控制晶体管中漏极电流的温度依赖性极弱
  • DOI:
    10.1002/aelm.202201163
  • 发表时间:
    2022
  • 期刊:
  • 影响因子:
    6.2
  • 作者:
    Bestelink E
  • 通讯作者:
    Bestelink E
High gain complementary inverters based on comparably-sized IGZO and DNTT source-gated transistors
基于同等尺寸 IGZO 和 DNTT 源栅晶体管的高增益互补逆变器
Evidence of Improved Thermal Stability via Nanoscale Contact Engineering in IGZO Source-Gated Thin-Film Transistors
通过 IGZO 源栅薄膜晶体管的纳米级接触工程提高热稳定性的证据
Compact Unipolar XNOR/XOR Circuit Using Multimodal Thin-Film Transistors
  • DOI:
    10.1109/ted.2021.3103491
  • 发表时间:
    2021-10-01
  • 期刊:
  • 影响因子:
    3.1
  • 作者:
    Bestelink, Eva;de Sagazan, Olivier;Sporea, Radu A.
  • 通讯作者:
    Sporea, Radu A.
Promoting Low-Voltage Saturation in High-Performance a-InGaZnO Source-Gated Transistors
  • DOI:
    10.1109/ted.2023.3331668
  • 发表时间:
    2023-11-21
  • 期刊:
  • 影响因子:
    3.1
  • 作者:
    Bestelink,Eva;Niang,Kham M.;Sporea,Radu A.
  • 通讯作者:
    Sporea,Radu A.
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Radu Sporea其他文献

Analytical Models for Delay and Power Analysis of Zero-VGS Load Unipolar Thin-Film Transistor Logic Circuits
零 VGS 负载单极薄膜晶体管逻辑电路的延迟和功耗分析模型
Source-Gated Transistors for Power- and Area-Efficient AMOLED Pixel Circuits
用于高效节能和面积高效的 AMOLED 像素电路的源门晶体管
  • DOI:
    10.1109/jdt.2013.2293181
  • 发表时间:
    2014-11
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Xiaoli Xu;Radu Sporea;Xiaojun Guo
  • 通讯作者:
    Xiaojun Guo

Radu Sporea的其他文献

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{{ truncateString('Radu Sporea', 18)}}的其他基金

Multipurpose Electronics Toolkit using Suspended Membranes: towards Systems on Nothing
使用悬浮膜的多用途电子工具包:走向无源系统
  • 批准号:
    EP/Y000196/1
  • 财政年份:
    2024
  • 资助金额:
    $ 142.79万
  • 项目类别:
    Research Grant
Design for high-yield manufacturing of printed circuits
印刷电路高良率制造设计
  • 批准号:
    EP/R028559/1
  • 财政年份:
    2018
  • 资助金额:
    $ 142.79万
  • 项目类别:
    Research Grant

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