Device Process for Integrated Systems Composed of Dislocation-Free III-V-N Alloys and Silicon

无位错III-V-N合金和硅组成的集成系统的器件工艺

基本信息

  • 批准号:
    15002007
  • 负责人:
  • 金额:
    $ 200.51万
  • 依托单位:
  • 依托单位国家:
    日本
  • 项目类别:
    Grant-in-Aid for Specially Promoted Research
  • 财政年份:
    2003
  • 资助国家:
    日本
  • 起止时间:
    2003 至 2005
  • 项目状态:
    已结题

项目摘要

Basic process technologies have been developed for realizing novel optoelectronic integrated systems in a single chip, in which optical devices and electronic circuits were combined. These technologies were based on the dislocation-free heteroepitaxy of Si and III-V-N alloys.We have investigated point defects originated in N atoms in the III-V-N alloys and optical and electronic properties related to the defects. The defects were decreased by rapid thermal annealing and by suppressing the irradiation of N ions generated in an rf-plasma source. The effects led to the increase in photoluminescence intensity and the reduction of Ga interstitials. In addition, InGaPN layers with direct transition were successfully grown. It was clarified that the defects cause poor electronic conductivity. N-and p-type electronic conductivities were controlled by S and Mg doping, respectively.Si and III-V-N alloys were mutually impurities. Contamination during epitaxy was suppressed by applying a two-chamber molecular beam epitaxy system which was developed in this project. Process conditions for both devices of a Si MOS FET and a III-V-N alloy light emitting diode (LED) were optimized. Mutual diffusion between the Si and III-V-N alloy layers was suppressed by decreasing the growth temperature of a gate oxide. As a result, it became apparent that the novel optoelectronic integrated systems could be fabricated by applying a process flow followed to that of MOS integrated circuits.The composite layer of Si/III-V-N alloy double heterostructure (DH) layers was grown on a Si substrate. Elemental devices for the integrated systems, MOS FETs and LEDs, were fabricated in the topmost Si layer and the III-V-N alloy DH layer, respectively by applying the process flow for the first time. The optical output of the LED was controlled by the MOS FET. These results mean that the basic device process technologies were developed for the novel integrated systems such as ultra-parallel networks and others.
已经开发了基本的工艺技术来实现单个芯片中新型的光电集成系统,其中将光学设备和电子电路组合在一起。这些技术基于SI和IIII-V-N合金的无脱位异质。我们研究了点缺陷,起源于IIII-V-N合金中的N原子,以及与缺陷有关的光学和电子特性。通过快速的热退火和抑制在RF - 血浆源中产生的N离子的辐射来减少缺陷。效果导致光致发光强度的增加和GA间隙的降低。此外,具有直接过渡的INGAPN层已成功生长。澄清的是,缺陷会导致电子电导率差。 N和P型电子电导率分别通过S和MG掺杂控制。SI和IIII-V-N合金是相互杂质的。通过应用在该项目中开发的两腔分子束外延系统,抑制了外观上的污染。优化了SI MOS FET和IIII-V-N合金光(LED)的两个设备的工艺条件。 Si和IIII-V-N合金层之间的相互扩散通过降低栅极氧化的生长温度来抑制。结果,很明显,可以通过将过程流施加到MOS集成电路的过程流中来制造新型的光电集成系统。SI/IIII-V-N合金双重异质结构(DH)层的复合层是在SI上生长的基材。首次通过首次应用过程流,分别在最高的SI层和IIII-V-N合金DH层中制造了集成系统,MOS FET和LED的元素设备。 LED的光输出由MOS FET控制。这些结果意味着基本的设备工艺技术是针对新型集成系统(例如超平行网络和其他)开发的。

项目成果

期刊论文数量(40)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
K.Nishio, H.Yonezu, M.Ohtani, H.Yamada, Y.Furukawa: "Analog Metal-Oxide-Semiconductor Integrated Circuit Implementation of Approach Detection with Simple-Shape Recognition Based on Visual Systems of Lower Animals"Opt.Rev.. Vol.10,No.2. 96-105 (2003)
K.Nishio、H.Yonezu、M.Ohtani、H.Yamada、Y.Furukawa:“基于低等动物视觉系统的简单形状识别的接近检测的模拟金属氧化物半导体集成电路实现”Opt.Rev。
  • DOI:
  • 发表时间:
  • 期刊:
  • 影响因子:
    0
  • 作者:
  • 通讯作者:
Growth of B_xAl_<1-x>N Layers Using Decaborane on SiC Substrates
使用十硼烷在 SiC 衬底上生长 B_xAl_<1-x>N 层
Effect of Nitrogen Ion Bombardment on Defect Formation and Luminescence Efficiency of GaNP Epilayers Grown by Molecular-Beam Epitaxy
氮离子轰击对分子束外延生长的GaN外延层缺陷形成和发光效率的影响
  • DOI:
  • 发表时间:
    2006
  • 期刊:
  • 影响因子:
    0
  • 作者:
    D.Dagnelund;I.A.Buyanova;T.Mchedlidze;W.M.Chen;A.Utsumi;Y.Furukawa;A.Wakahara;H.Yonezu
  • 通讯作者:
    H.Yonezu
Effect of Indium on Photoluminescence Properties of InGaPN Layers Grown by Solid Source Molecular Beam Epitaxy
铟对固源分子束外延生长的InGaPN层光致发光性能的影响
A.Utsumi, H.Yonezu, Y.Furukawa, K.Momose, K.Kuroki: "Increase in luminescence efficiency of GaPN layers by thermal annealing"Phys.Stat.Sol.(c). Vol.0,No.7. 2741-2744 (2003)
A.Utsumi、H.Yonezu、Y.Furukawa、K.Momose、K.Kuroki:“通过热退火提高 GaPN 层的发光效率”Phys.Stat.Sol.(c)。
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  • 影响因子:
    0
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YONEZU Hiroo其他文献

YONEZU Hiroo的其他文献

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{{ truncateString('YONEZU Hiroo', 18)}}的其他基金

Massively Parallel Intelligent Preprocessing
大规模并行智能预处理
  • 批准号:
    13023205
  • 财政年份:
    2000
  • 资助金额:
    $ 200.51万
  • 项目类别:
    Grant-in-Aid for Scientific Research on Priority Areas
Implementation of Analog Integrated Circuits for Motion-Detection Network Based on Retina and Brain
基于视网膜和大脑的运动检测网络模拟集成电路的实现
  • 批准号:
    11555013
  • 财政年份:
    1999
  • 资助金额:
    $ 200.51万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Fabrication of Functional Heteroepitaxial Layers Embedding Devices
功能性异质外延层嵌入装置的制造
  • 批准号:
    11450011
  • 财政年份:
    1999
  • 资助金额:
    $ 200.51万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Research on a vision chip based on biological systems
基于生物系统的视觉芯片研究
  • 批准号:
    09045052
  • 财政年份:
    1997
  • 资助金额:
    $ 200.51万
  • 项目类别:
    Grant-in-Aid for international Scientific Research
Fundamental Study of Nitride Semiconductor Materials for UV-Wavelength Laser Diode
紫外波长激光二极管氮化物半导体材料的基础研究
  • 批准号:
    08455037
  • 财政年份:
    1996
  • 资助金额:
    $ 200.51万
  • 项目类别:
    Grant-in-Aid for Scientific Research (B)
Massively Parallel Optical Interconnection for Realization of Three-Dimensional Integrated Circuits
用于实现三维集成电路的大规模并行光互连
  • 批准号:
    07555014
  • 财政年份:
    1995
  • 资助金额:
    $ 200.51万
  • 项目类别:
    Grant-in-Aid for Scientific Research (A)
Basic Research on Optoelectronic Devices for Neural Networks
神经网络光电器件基础研究
  • 批准号:
    01460082
  • 财政年份:
    1989
  • 资助金额:
    $ 200.51万
  • 项目类别:
    Grant-in-Aid for General Scientific Research (B)

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