A Psychologically-Inspired VLSI Brain Model System Implementing Subconscious Information Processing Based on Analog/Digital Marged Computation

基于模拟/数字边缘计算实现潜意识信息处理的受心理启发的VLSI大脑模型系统

基本信息

  • 批准号:
    14205043
  • 负责人:
  • 金额:
    $ 32.45万
  • 依托单位:
  • 依托单位国家:
    日本
  • 项目类别:
    Grant-in-Aid for Scientific Research (A)
  • 财政年份:
    2002
  • 资助国家:
    日本
  • 起止时间:
    2002 至 2004
  • 项目状态:
    已结题

项目摘要

The purpose of this research is to develop a human-like flexible recognition system not by a sophisticated software processing but by developing VLSI hardware most efficiently mimicking the "human mind-processing".The core of the system is the associative processor that autonomously recalls the maximum likelihood event in the past experience to a current input. We have developed an associative processor where the polarization in a ferroelectric film is utilized as the memory media in the system. In order to resolve the problem of depolarization in the film and the resultant degraded memory contents, a newly developed "Hetero-Gate Ferroelectric Floating Gate MOS" device was introduced to build associative circuitries. Experimental investigation on the ferroelectric film characteristics in such applications has been extensively conducted and it was shown that the system is most suited to such applications as mobile systems in which power dissipation is severely limited. ADP matching VLSI … More chip has been developed for episode memory recall. In episode memory, time sequences of events are stored and the most similar sequence needs be searched allowing some missing events or insertion of some extra events. This is a very computationally expensive processing. However, a very low-power and high-speed DP matching VLSI has been developed based on delay-encoding logic circuits. The system deals analog signals in the time domain while digital signals are utilized in the voltage domain, resulting in the fast and low power operation.As a test vehicle of algorithm development, a face localization and verification system has been developed. Using the image feature vectors based on the edge information extracted from images, faces are very robustly detected from various scenes under different illumination, defocusing, scaling and rotation conditions. Since edge filtering is a very computationally expensive processing, various VLSI chips specialized for the processing have been developed and real-time response capability has been achieved. By operating the image vector generation VLSI at only 100MHz, it outperforms the software processing running on a PC having 2GHz CPU by a factor of approximately 10,000. Less
这项研究的目的是开发一个类似人类的灵活识别系统,而不是通过复杂的软件处理,而是通过开发VLSI硬件最有效地模仿“人类思维精神处理”。该系统的核心是自动回忆到过去输入中最大可能的可能性的关联处理器。我们已经开发了一个关联处理器,其中将铁电膜中的极化用作系统中的存储介质。为了解决膜中的沉积问题和由此产生的降级记忆内容物,引入了新开发的“异型栅极铁电浮栅门MOS”设备以构建关联电路。对此类应用中铁电膜特征的实验研究已经进行了广泛的进行,并且表明该系统最适合诸如极限限制功率的移动系统等应用。 ADP匹配VLSI…已开发了更多芯片以供情节记忆回忆。在情节内存中,存储事件的时间序列,并且需要搜索最相似的序列,以允许一些丢失的事件或插入一些额外的事件。这是一个非常昂贵的处理。但是,基于延迟编码的逻辑电路开发了非常低的功率和高速DP匹配VLSI。该系统在电压域中使用数字信号时在时间域中处理模拟信号,从而导致快速和低功率操作。作为算法开发的测试工具,已经开发了面部定位和验证系统。使用基于从图像中提取的边缘信息的图像特征向量,从不同的照明,散落,缩放和旋转条件下的各种场景中检测到面孔。由于边缘过滤是一种非常昂贵的处理,因此已经开发了专门用于处理的各种VLSI芯片,并实现了实时响应能力。通过仅在100MHz的情况下操作图像矢量生成VLSI,它的表现优于在具有2GHz CPU的PC上运行的软件处理约为10,000倍。较少的

项目成果

期刊论文数量(102)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
Simple-Architecture Motion-Detection Analog VLSI Based on Quasi-Two-Dimensional Processing
基于准二维处理的简单结构运动检测模拟VLSI
Qian-Rong Gu, Tadashi Shibata: "Speaker and Text Independent Language identification Using Predictive Error Histogram Vectors"Proc. 2003 International Conference on accepted for presentation Acoustics, Speech, and Signal Processing (ICASSP). I36-I39 (2003
顾千荣,柴田正:“使用预测误差直方图向量进行与说话者和文本无关的语言识别”Proc。
  • DOI:
  • 发表时间:
  • 期刊:
  • 影响因子:
    0
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  • 通讯作者:
H.Yamasaki, T.Shibata: "A Real-Time VLSI Median Filter Employing Two-Dimensional Bit-Propagating Architecture"Proc.2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). (印刷中). (2004)
H.Yamasaki、T.Shibata:“采用二维位传播架构的实时 VLSI 中值滤波器”Proc.2004 IEEE 国际电路与系统研讨会 (ISCAS 2004)(印刷中)。
  • DOI:
  • 发表时间:
  • 期刊:
  • 影响因子:
    0
  • 作者:
  • 通讯作者:
A Floating-Gate-MOS-Based Low-Power CDMA Matched Filter Employing Capacitance Disconnection Technique,
一种采用电容断开技术的基于浮栅 MOS 的低功耗 CDMA 匹配滤波器,
High-Precision Metal-on-Insulator Micro Spires for Use in Non-magnetic-Probe Magnetic Microscopy,
用于非磁性探针磁力显微镜的高精度绝缘体上金属微型尖顶,
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SHIBATA Tadashi其他文献

SHIBATA Tadashi的其他文献

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{{ truncateString('SHIBATA Tadashi', 18)}}的其他基金

A VLSI Brain System Integrating Massively-Parallel Subconscious Processing With Sequential Conscious Processing in the Mind
一种将大规模并行潜意识处理与大脑中的顺序意识处理相结合的 VLSI 大脑系统
  • 批准号:
    20246056
  • 财政年份:
    2008
  • 资助金额:
    $ 32.45万
  • 项目类别:
    Grant-in-Aid for Scientific Research (A)
A Motion-Analysis VLSI Image Sensor System Extracting the Meaning of Action From Moving Images
运动分析 VLSI 图像传感器系统从运动图像中提取动作的含义
  • 批准号:
    17206030
  • 财政年份:
    2005
  • 资助金额:
    $ 32.45万
  • 项目类别:
    Grant-in-Aid for Scientific Research (A)
An Intelligent Image-Recognition VLSI System Employing Neuron-MOS Feature Extracting Circuitry
采用Neuron-MOS特征提取电路的智能图像识别VLSI系统
  • 批准号:
    11305024
  • 财政年份:
    1999
  • 资助金额:
    $ 32.45万
  • 项目类别:
    Grant-in-Aid for Scientific Research (A)
A NEURON-MOS NEURAL NETWORK FEATURING ON-CHIP SELF-LEARNING CAPABILITY
具有片上自学习功能的 NEURON-MOS 神经网络
  • 批准号:
    05505003
  • 财政年份:
    1993
  • 资助金额:
    $ 32.45万
  • 项目类别:
    Grant-in-Aid for Developmental Scientific Research (A)
NEW LOGIC LSI'S HAVING SOFT HARDWARE CONFIGURATION
具有软硬件配置的新逻辑LSI
  • 批准号:
    04402029
  • 财政年份:
    1992
  • 资助金额:
    $ 32.45万
  • 项目类别:
    Grant-in-Aid for General Scientific Research (A)
A New Functional MOS Transistor Featuring Neuron Functions
一种具有神经元功能的新型功能 MOS 晶体管
  • 批准号:
    02402032
  • 财政年份:
    1990
  • 资助金额:
    $ 32.45万
  • 项目类别:
    Grant-in-Aid for General Scientific Research (A)
RF-DC Coupled Mode Bias Sputtering System
RF-DC耦合模式偏压溅射系统
  • 批准号:
    62850050
  • 财政年份:
    1987
  • 资助金额:
    $ 32.45万
  • 项目类别:
    Grant-in-Aid for Developmental Scientific Research

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SHF: Small: A General-purpose Parallel and Heterogeneous Task Graph Computing System for VLSI CAD
SHF:小型:用于 VLSI CAD 的通用并行异构任务图计算系统
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    2349141
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    2023
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SHF: Small: A General-purpose Parallel and Heterogeneous Task Graph Computing System for VLSI CAD
SHF:小型:用于 VLSI CAD 的通用并行异构任务图计算系统
  • 批准号:
    2126672
  • 财政年份:
    2021
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Development of fully autonomous error-correctable VLSI design technology and its application to brain-inspired LSI system
全自主可纠错VLSI设计技术开发及其在类脑LSI系统中的应用
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    16KT0187
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基于功能记忆的VLSI系统生长和适应环境的研究
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