Design for Fault Tolerant VLSI Chips

容错VLSI芯片设计

基本信息

批准号：
10650331
负责人：
ITO Hideo
金额：
$ 2.5万
依托单位：
Chiba University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 2000
项目状态：
已结题

项目摘要

The target of this research was to develop the techniques making chip yield increase for fabrication and making chip fault tolerance during notmal operation for general purpose VLSI chip which would be used after ten years. The technieques were developed in the architecture design, logical design, and circuit design. We have got the following results.(1) Reconfiguration method for defects and faultsWe have got the following 3 resuts for defect and fault tolerance in reconfiguring FPGA chips. (1.1) Reconfiguration designs against defects and faults in CLB (Configuration Logic Block), (1.2) Reconfiguration designs against defects and faults in wiring area, and (1.3) Diagnosis and Reconfiguration designs against defects and faults in SRAM.(2) Easily testable logic designWe have got the following 3 resuts. (2.1) Short test sequence generation for sequential circuits by connecting test vectors using a state transition diagram, (2.2) FF selection method for partial scan FFs, A study for the relation between reset FFs and fault coverage, and BIST (Built-In Self-Test) using check points, and (2.3) FPGA design and test generation for the high speed testing.(3) Architecure design for easy error recoveryWe have got the following 4 resuts. (3.1) LPU-MPU architecture design for LPU-MPU-HPU, 3-lebel hierarchical, parallel processing system, (3.2) Checkpointing method for error recovery in parallel processing systems, (3.3) Multiple mode system design with high reliable mode and normal modes, and (3.4) Routing algorithms for parallel systems with faults in nodes or links.

这项研究的目标是开发使制造芯片产量提高的技术，并在诺玛尔运行期间用于通用芯片芯片，这将在十年后使用。这些技术是在建筑设计，逻辑设计和电路设计中开发的。我们得到了以下结果。（1）在重新配置FPGA芯片时，用于缺陷的重新配置方法和Furdswe有以下3个用于缺陷和错误耐受性的重置。（1.1）针对CLB（配置逻辑块）中的缺陷和故障的重新配置设计，（1.2）针对接线区域的缺陷和故障的重新配置设计，以及（1.3）诊断和重新配置设计，以防止缺陷和重新配置设计，以防止缺陷和SRAM中的缺陷和故障。（2）易于测试的逻辑设计。（2.1）通过使用状态过渡图，（2.2）部分扫描FF的FF选择方法连接测试向量的短期测试序列生成，用于重置FFS和故障覆盖范围之间的关系的研究，以及使用检查点（2.3）fpga设计和测试的型号进行了高速测试，以进行高速级别的测试。 (3.1) LPU-MPU architecture design for LPU-MPU-HPU, 3-lebel hierarchical, parallel processing system, (3.2) Checkpointing method for error recovery in parallel processing systems, (3.3) Multiple mode system design with high reliable mode and normal modes, and (3.4) Routing algorithms for parallel systems with faults in nodes or links.