Design for Fault Tolerant VLSI Chips

容错VLSI芯片设计

基本信息

批准号：
10650331
负责人：
ITO Hideo
金额：
$ 2.5万
依托单位：
Chiba University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
1998
资助国家：
日本
起止时间：
1998 至 2000
项目状态：
已结题

项目摘要

The target of this research was to develop the techniques making chip yield increase for fabrication and making chip fault tolerance during notmal operation for general purpose VLSI chip which would be used after ten years. The technieques were developed in the architecture design, logical design, and circuit design. We have got the following results.(1) Reconfiguration method for defects and faultsWe have got the following 3 resuts for defect and fault tolerance in reconfiguring FPGA chips. (1.1) Reconfiguration designs against defects and faults in CLB (Configuration Logic Block), (1.2) Reconfiguration designs against defects and faults in wiring area, and (1.3) Diagnosis and Reconfiguration designs against defects and faults in SRAM.(2) Easily testable logic designWe have got the following 3 resuts. (2.1) Short test sequence generation for sequential circuits by connecting test vectors using a state transition diagram, (2.2) FF selection method for partial scan FFs, A study for the relation between reset FFs and fault coverage, and BIST (Built-In Self-Test) using check points, and (2.3) FPGA design and test generation for the high speed testing.(3) Architecure design for easy error recoveryWe have got the following 4 resuts. (3.1) LPU-MPU architecture design for LPU-MPU-HPU, 3-lebel hierarchical, parallel processing system, (3.2) Checkpointing method for error recovery in parallel processing systems, (3.3) Multiple mode system design with high reliable mode and normal modes, and (3.4) Routing algorithms for parallel systems with faults in nodes or links.

本研究的目标是为十年后使用的通用VLSI芯片开发提高芯片制造良率和在正常运行期间芯片容错的技术。这些技术在架构设计、逻辑设计和电路设计方面得到了发展。我们得到了以下结果。 (1)缺陷和故障的重配置方法针对FPGA芯片的缺陷和容错的重配置，我们得到了以下3种结果。 (1.1)针对CLB(配置逻辑块)中的缺陷和故障的重配置设计，(1.2)针对布线区域中的缺陷和故障的重配置设计，以及(1.3)针对SRAM中的缺陷和故障的诊断和重配置设计。(2)易于测试逻辑设计我们得到了以下3个结果。 (2.1) 通过使用状态转换图连接测试向量来生成时序电路的短测试序列，(2.2) 部分扫描 FF 的 FF 选择方法，复位 FF 与故障覆盖率之间关系的研究以及 BIST（内置自测试） -测试）使用检查点，以及（2.3）用于高速测试的FPGA设计和测试生成。（3）易于错误恢复的架构设计我们得到了以下4个结果。 (3.1) LPU-MPU-HPU、3级分层并行处理系统的LPU-MPU架构设计，(3.2)并行处理系统中错误恢复的检查点方法，(3.3)高可靠模式和正常模式的多模式系统设计模式，以及（3.4）节点或链路故障的并行系统的路由算法。