Design for Fault-Tolerant Programmable Chips

容错可编程芯片的设计

基本信息

批准号：
13650370
负责人：
ITO Hideo
金额：
$ 2.05万
依托单位：
Chiba University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (C)
财政年份：
2001
资助国家：
日本
起止时间：
2001 至 2003
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/grant/KAKENHI-PROJECT-13650370/
关键词：
FPGA Programmable Chip Defect Defect Tolerance Fault Detection Reconfiguration Error Recovery マルチコンテキスト SOC カバリッジ

项目摘要

We have got the following results concerning (1),(2),(3),and (4).(1)Defect Tolerant DesignWe proposed a defect and fault tolerant design for SOC, which is built by cores having the heterogenieous structutures. We proved the efficiency of our design by numerical evaluation results. We also proposed a defect and fault tolerant design for SOC consisting of cores which arc built in hierachical manner and where the lowest level circuits have homogenious structures. We applied our strategy to 32-bits parallel multiplier to show the efficiency of our design.(2)FPGA TestingA test method for mufti-context FPGA has been proposed. This method has the advantage of having small number of writing times for configuration memory. In this context, survey for conventional works about FPGA testing, defect and fault tolerant designs have been made.(3)VISI TestingWe have investigated the following directions of research in testing: a design for BISTs for delay fault detection and analysis of delay fault detection, two test methods using programmable cores in SOC for testing circuits under the test, and design of BIST for SOC which are made in hierarchical structure.(4)Architecture for Fault Tolerance and RecoveringWe proposed an easily recovering method from deadlock in an interconnection network We evaluated the performance by the analysis of the network In this area of research fault tolerant routing in an interconnection network and fault tolerant wormhole-based switching making possible backtracking have been proposed.

我们得到了以下关于(1)、(2)、(3)和(4)的结果。 (1)缺陷容错设计我们提出了一种由具有异构结构的内核构建的SOC的缺陷和容错设计。我们通过数值评估结果证明了我们设计的效率。我们还提出了一种由以分层方式构建的内核组成的 SOC 的缺陷和容错设计，其中最低级电路具有同质结构。我们将我们的策略应用到32位并行乘法器中以展示我们设计的效率。(2)FPGA测试提出了一种多上下文FPGA的测试方法。该方法的优点是配置存储器写入次数少。在此背景下，对FPGA测试、缺陷和容错设计等传统工作进行了综述。(3)VISI测试我们在测试方面研究了以下方向：用于延迟故障检测的BIST设计和延迟故障检测分析。，使用SOC中的可编程内核来测试被测电路的两种测试方法，以及分层结构的SOC的BIST设计。（4）容错和恢复架构我们提出了一种从互连死锁中轻松恢复的方法网络我们通过分析网络来评估性能在这一研究领域中，互连网络中的容错路由和基于虫洞的容错交换使得回溯成为可能。