The Development of Basic Software Techniques for Variable-Voltage Processors Targeting Low-Energy Consumption

面向低能耗的变压处理器基础软件技术开发

基本信息

批准号：
12558029
负责人：
YASUURA Hiroto
金额：
$ 8.51万
依托单位：
Kyushu University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Scientific Research (B)
财政年份：
2000
资助国家：
日本
起止时间：
2000 至 2001
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-12558029/
关键词：
Low Energy System on a Chip Variable Voltage Embedded System System Software Processor Architecture Memory

项目摘要

This work discusses some basic techniques of software for variable-voltage processors in order to realize low-energy design, together with modeling techniques and evaluations of their potential benefits by simulation. Details are listed as follows :1) A task scheduling technique for a real-time system with a variable-voltage processor, by which supply voltage is changed dynamically, is presented.2) A platform for datapath width optimization of soft-core processors is built and the presented methodology of datapath optimization is evaluated by using MPEG AAC decoder. In addition, an energy minimization methodology using datapath width optimization is proposed. To find the optimized datapath width for a given application in the early phase of designs, an effective bitwidth and access frequency of variables based performance estimation technique is also developed. A low-energy memory design technique is presented as well.3) A new datapath width optimization methodology considering computation precision targeting area and power reduction is presented.4) A power reduction technique by reducing switching of redundant bit is presented, here effective bit line on data bus is called active bit, the other bit is called redundant bit.5) A cost model for SoC (System on a Chip), in which each cost as a parameter is presented, and a design method by market scale and number of products is also presented.6) High-performance/low power cache architectures with variable cache-line size for merged DRAM/Logic LSIs are presented ; in addition, a low-power instruction cache architecture exploiting program execution footprints is presented.

这项工作讨论了一些用于可变电压处理器的软件的基本技术，以实现低能设计，并通过模拟技术进行建模技术和对其潜在益处的评估。详细信息如下：1）具有可变电压处理器的实时系统的任务调度技术，通过动态更改供应电压。2）构建了用于dataPath宽度优化软核处理器的平台，并构建了数据PECORE处理器的宽度宽度，并通过使用MPEG AAC AAC AAC DECODERER来评估数据PAPATH的方法。另外，提出了使用DataPath宽度优化的能量最小化方法。为了在设计的早期阶段找到给定应用的优化数据宽度，还开发了基于变量的性能估计技术的有效位宽度和访问频率。 3）提出了一种新的数据宽宽度优化方法，考虑计算精确的靶向区域和降低功率。4）通过减少冗余位的切换来减少功率减少技术，在这里，有效的位上的位上的位上的有效位线在数据总线上被称为活跃位，另一个是冗余的。还提出了按市场规模和产品数量进行的设计方法。6）提出了合并DRAM/LOGIC LSIS的高性能/低功率缓存架构；此外，还提供了低功率指令缓存架构，利用程序执行足迹。