Research on Logic Synthesis and Hardware Description Language Considering Layout Design

考虑布局设计的逻辑综合与硬件描述语言研究

基本信息

批准号：
04452198
负责人：
YASUURA Hiroto
金额：
$ 4.54万
依托单位：
Kyushu Univ.
依托单位国家：
日本
项目类别：
Grant-in-Aid for General Scientific Research (B)
财政年份：
1992
资助国家：
日本
起止时间：
1992 至 1993
项目状态：
已结题

来源：
https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-04452198/
关键词：
VLSI CAD Placement and Routing, Hardware Description Language Hardware Software Codesign Login Synthesis Microprocessor Soft Core-Processor Layout Synthesis ソフトコアプロセッサレイアウト設計配線遅延

项目摘要

Traditional logic synthesis technology principally aims at generating topological information of logic circuits, realizing function given by functional description. Geometric information which appears in a final mask-pattern is decided in layout synthesis stage independently from logic synthesis. Therefore, in the case of random circuits like control-path, it is possible to get better performance than manual design. But, in the case of regular circuits like data-path, iti is hard to design good synthesis method in which geometric restriction on layout is considered in logic synthesis, and a design description language for that purpose.(a) Study on design description language that canrepresent regularity of layout-pattern : We proposed a language which can specigy the regularity on layout-pattern and the outline of placement and routing information in functional design.(b) Study on logic synthesis considering areas and wiring delays : We investigated a logic sythesis method considering wiring delays and areas in logic synthesis, and proposed a circuit synthesis method using the commutative law.(c) Comparisons of methods to design the practical circuits : We examined the effect of the several synthesis methods, applying them to practical development of a microprocessor. We concretely point out problems on commercial tools and languages.(d) Applocation of the logic synthesis method : As an application of our method, we propose hardware/software codesign using soft core-processor.Through the above researches, we unified logic synthesis and layout synthesis, which have been done independently. In our method, designers specify information on layout in architecture design, and logic synthesis and layout synthesis are done using its information. We also show a framework of new design automation system and its application method.

传统的逻辑合成技术主要旨在生成逻辑电路的拓扑信息，从而实现功能描述给出的功能。最终蒙版模式中出现的几何信息是在布局合成阶段决定的，独立于逻辑合成。因此，在控制路径（例如控制路径）等随机电路的情况下，可以比手动设计获得更好的性能。 But, in the case of regular circuits like data-path, iti is hard to design good synthesis method in which geometric restriction on layout is considered in logic synthesis, and a design description language for that purpose.(a) Study on design description language that canrepresent regularity of layout-pattern : We proposed a language which can specigy the regularity on layout-pattern and the outline of placement and routing information in functional design.(b) Study on逻辑综合考虑区域和布线延迟：我们研究了一种逻辑学方法，考虑了逻辑合成中的布线延迟和区域，并提出了使用交换定律的电路合成方法。（c）设计实际电路的方法的比较：我们检查了几个合成方法的效果，以实用这些合成方法的效果，以实践微米的开发。我们具体地指出了商业工具和语言上的问题。（d）逻辑合成方法的使用：作为我们方法的应用，我们使用软核心过程提出了硬件/软件代码。通过上述研究，我们统一了独立完成的逻辑综合和布局合成。在我们的方法中，设计人员指定了有关架构设计中布局的信息，并使用其信息完成了逻辑合成和布局综合。我们还展示了新设计自动化系统及其应用方法的框架。