Performance Improvement by Exploiting Instruction-Level Parallelism

通过利用指令级并行性来提高性能

• 批准号: 02452166
• 负责人: TOMITA Shinji
• 金额: $ 3.65万
• 依托单位: Kyoto University (1991)Kyushu University (1990)
• 依托单位国家: 日本
• 项目类别: Grant-in-Aid for General Scientific Research (B)
• 财政年份: 1990
• 资助国家: 日本
• 起止时间: 1990 至 1991
• 项目状态: 已结题
• 来源: https://kaken.nii.ac.jp/en/grant/KAKENHI-PROJECT-02452166/
• 关键词: Superscalar processor; Instruction pipeline; Optimized compiler; Code scheduling; Branch prediction; Load; store architecture; Interrupt architecture; Low-level parallelism; ス-パ-スカラ・プロセッサ

The purpose of this research is to exploit parallelism at instruction level and to investigate various performance improvement techniques for superscalar architecture. Main results of the research are the following :l. Basic control mechanism for superscalar processorVarious techniques for improving the performance are proposed and verified to be effective by software simulation. These techniques include ; (1) Four-instruction-multiplexed pipelining scheme with in-order issue and out-of-order execution strategy. This scheme not only attains high-speed execution but also reduces hardware cost drastically. (2) Powerful branch prediction mechanism in which the branch target buffer and static branch prediction methods are combined. Together with the early branch resolution, this gives a great contribution to preventing control hazards. (3) New mechanism to escape imprecise interruption, (4) Static resolution method against load/store hazards.2. Optimizing compilerOptimizing compiler plays an essential role in improving the performance of superscalar processor. A software pipeline scheme, a loop-unrolling scheme and a powerful combination of these schemess are investigated and verified to be effective by simulation. Maximally 5 times higher performance can be gained.

这项研究的目的是在教学层面上利用并行性，并研究超级尺度体系结构的各种绩效改进技术。研究的主要结果如下：l。提出并通过软件模拟进行了超级加工技术的基本控制机制，以改善性能。这些技术包括： （1）具有固定问题和置换执行策略的四个指导方式管道方案。该方案不仅可以达到高速执行，而且还大大降低了硬件成本。 （2）将分支目标缓冲区和静态分支预测方法组合的强大分支预测机制。与早期的分支解决方案一起，这为防止控制危害做出了巨大贡献。 （3）逃避不精确中断的新机制，（4）针对负载/商店危害的静态分辨率方法2。优化编译器的编译器在改善超级处理器的性能中起着至关重要的作用。对软件管道方案，循环未汇编方案和这些图案的强大组合进行了研究，并通过仿真进行了验证。最大的性能可以提高5倍。

项目成果

Kazuaki Murakami: "Trade-offs in Processor Design for Superscalar Architectures" Trans. IEICE. 74. 3883-3893 (1991)

Kazuaki Murakami：“超标量架构处理器设计的权衡”Trans。

久我 守弘: "SIMP(単一命令流/多重命令パイプライン)方式に基づくス-パスカラ・プロセッサ『新風』の性能評価" 情報処理学会「並列処理シンポジウムJSPP'90」. 337-344 (1990)

Morihiro Kuga：“基于 SIMP（单指令流/多指令管道）方法的超标量处理器“Shinpu”的性能评估”日本信息处理协会“并行处理研讨会 JSPP90”（1990）。

Akira Fukuda: "Toward Advanced Parallel Processing:Exproiting Parallelism at Task and Instruction Levels" IEEE MICRO. August. 17-31 (1991)

Akira Fukuda：“迈向高级并行处理：在任务和指令级别利用并行性”IEEE MICRO。

久我 守弘: "SIMP(単一命令流/多重命令パイプライン)方式に基づくス-パスカラ・プロセッサ『新風』の性能評価" 情報処理学会論文誌. 32. 817-827 (1991)

Morihiro Kuga：“基于 SIMP（单指令流/多指令管道）方法的超标量处理器“Shinpu”的性能评估”日本信息处理协会交易 32. 817-827（1991）。

Morihiro Kuga: "Performance Evaluation of the Superscalar Processor Based on the SIMP Architecture" Trans. IPSJ. 32. 817-827 (1991)

Morihiro Kuga：《基于SIMP架构的超标量处理器性能评估》Trans。