Development of a High-Performance Workstation with a Very-Long-Instruction-Word (VLIW) Processor

开发具有超长指令字 (VLIW) 处理器的高性能工作站

基本信息

批准号：
62850062
负责人：
TOMITA Shinji
金额：
$ 14.85万
依托单位：
Kyushu University
依托单位国家：
日本
项目类别：
Grant-in-Aid for Developmental Scientific Research
财政年份：
1987
资助国家：
日本
起止时间：
1987 至 1988
项目状态：
已结题

项目摘要

Main results of the project are summarized below.1. Evaluation of the QA-series and Redesign of VLIW Architecture:VLIW (Very Long Instruction Word) processors, such as the QA-series, can exploit low-level parallelism in the process of instruction execution. However, they have a serious drawback; i.e., it is difficult for VLIW architectures to keep program compatibility, because their architectures are exposed to compilers. As a result of the evalution, we have introduced a novel processor architecture, SIMP (Single Instruction stream/Multiple instruction Pipelining), as a deviation of VLIW. Given that P instruction pipelines are provided, SIMP porcessors ideally reduce the average number of cycles per instruction to 1/p by fetching P instructions per cycle. they can preserve program compatibility at the same time.2. Development of the SIMP Processor Prototype:As the first implementation of SIMP, we have developed the SIMP processor prototype. Degree of performance enhancement achieved by SIMP depends on; i) how to supply multiple instructions continuously and simultaneously, and ii) how to resolve data and control dependencies effectively. We have devised the algorithms for dependency resolution and instruction fetch. The dependency resolution algorithm permits out-of-order execution of sequential instruction stream with dynamic code scheduling.3. Studies on Static code Scheduling:Though the prototype employs dynamic code scheduling, it appreciates the advantage of static code scheduling. Static and dynamic code scheduling methods differ in their domain; i.e., static code scheduling is done with a broad overview of program codes, but dynamic code scheduling is done with a peephole. However, these code scheduling methods are not mutually exclusive. We have studied the adaptability of static code scheduling such as trace scheduling, software pipelining, polycyclic scheduling, and so on.

该项目的主要结果总结为1。评估VLIW体系结构的QA系列和重新设计：VLIW（非常长的指令单词）处理器，例如QA系列，可以在执行指令执行过程中利用低级并行性。但是，他们有一个严重的缺点。即，VLIW架构很难保持程序兼容性，因为它们的体系结构暴露于编译器。评估的结果是，我们引入了一种新型的处理器体系结构SIMP（单个指令流/多个指令管道），作为VLIW的偏差。鉴于提供了P指令管道，SIMP院士理想地通过每个周期获取P指令，将每个指令的平均周期数减少到1/P。他们可以同时保留程序兼容性2。 SIMP处理器原型的开发：作为SIMP的首次实现，我们开发了SIMP处理器原型。 SIMP实现的性能增强程度取决于； i）如何连续，同时提供多个指令，以及ii）如何有效地解决数据和控制依赖性。我们已经设计了依赖关系和指令提取的算法。依赖项分辨率算法允许使用动态代码调度进行顺序指令流的截面执行。3。静态代码调度的研究：尽管该原型采用动态代码调度，但它赞赏静态代码调度的优势。静态和动态代码调度方法在其域上有所不同。即，静态代码调度是通过对程序代码进行广泛概述完成的，但是动态代码调度是用窥视台完成的。但是，这些代码调度方法不是相互排斥的。我们已经研究了静态代码调度的适应性，例如跟踪调度，软件管道，多环切计划等。