III-V semiconductor nanowires: correlation of local electronic structure, conductivity, and carrier lifetime

III-V族半导体纳米线：局部电子结构、电导率和载流子寿命的相关性

• 批准号: 390247238
• 负责人: Professor Dr. Mario Dähne, since 5/2021
• 金额: --
• 依托单位: Institut dÉlectronique de Microélectronique et de Nanotechnologie (IEMN)
• 依托单位国家: 德国
• 项目类别: Research Grants
• 财政年份: 2018
• 资助国家: 德国
• 起止时间: 2017-12-31 至 2022-12-31
• 项目状态: 已结题
• 来源: https://gepris.dfg.de/gepris/projekt/390247238?language=en
• 关键词: III; semiconductor; nanowires; correlation; local

Semiconductor nanowires (NW) are promising building blocks of novel electronic and optoelectronic devices, with an exceptional wide range for tailoring electronic properties by size, geometry, and different crystallographic structures. Even crystallographic structures being not available as bulk materials can be produced. Hence, NWs are considered for many potential applications ranging from solar cells to nanoelectronics. However, many fundamental aspects remain to be elucidated. Two of them are particularly relevant: First, the NW geometry leads to a very high surface-to-volume ratio. Consequently, surface-induced effects, such as Fermi level pinning, play a large role for the properties of NWs and the functionality of devices based on them. Second, NWs may contain frequently polytype insertions, twin boundaries, and stacking faults in addition to intentionally inserted heterointerfaces. They affect the electronic properties, introduce band offsets, and hence influence the conductivity and carrier lifetimes. Therefore, the overall objective of this project is to investigate the electronic properties of sidewall surfaces, defects, and interfaces with atomic resolution, and correlate them with conductivity and carrier lifetimes of III-V semiconductor NWs.In particular, we plan to investigate in a first step (i) the possible Fermi level pinning, the energetic position, and its physical origin at the sidewall surfaces of different III-V material compositions and for different polytypes, (ii) the interface states, band alignments and offsets, as well as band gaps near heterointerfaces, (iii) the electronic properties of planar defects and polytype insertions, and (iv) the interaction of the surface Fermi level pinning with internal junctions, interfaces, and defects. In a second step, these properties will be correlated with the conductivity and carrier lifetimes of NWs. The main objectives are to elucidate, how an extrinsic surface pinning, interfaces as well as planar defects, and intentionally incorporated point defects affect conductivity and carrier lifetimes of NWs.

半导体纳米线（NW）是新型电子和光电设备的有前途的构建块，其范围非常广泛，可根据大小，几何形状和不同的晶体学结构来定制电子性能。甚至可以生产散装材料，甚至无法获得晶体学结构。因此，对于从太阳能电池到纳米电子的许多潜在应用，也考虑了NW。但是，许多基本方面仍有待阐明。其中两个特别相关：首先，NW几何形状导致表面与体积的比率很高。因此，表面诱导的效应（例如费米级固定）对NWS的性质和基于它们的设备的功能起着重要作用。其次，除了有意插入的异质方面外，NWS可能经常包含多型插入，双边界和堆叠故障。它们会影响电子特性，引入带偏移，从而影响电导率和载体寿命。 Therefore, the overall objective of this project is to investigate the electronic properties of sidewall surfaces, defects, and interfaces with atomic resolution, and correlate them with conductivity and carrier lifetimes of III-V semiconductor NWs.In particular, we plan to investigate in a first step (i) the possible Fermi level pinning, the energetic position, and its physical origin at the sidewall surfaces of different III-V material compositions and for different多型，（ii）界面状态，带对齐和偏移，以及附近的异质空间，（iii）平面缺陷和多型插入的电子特性，以及（iv）表面FERMI水平与内部连接，接口，接口和缺陷的相互作用。在第二步中，这些特性将与NWS的电导率和载体寿命相关。主要目标是阐明外部表面固定，界面以及平面缺陷以及故意合并点缺陷会影响NWS的电导率和载体寿命。