IRES Track I: Development of Global Scientists and Engineers by Collaborative Research on Reliability-Aware IC Design

IRES Track I：通过可靠性意识 IC 设计合作研究促进全球科学家和工程师的发展

基本信息

批准号：
1854276
负责人：
Sheldon Tan
金额：
$ 30万
依托单位：
University of California-Riverside
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2019
资助国家：
美国
起止时间：
2019-04-01 至 2023-03-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1854276&HistoricalAwards=false
关键词：
IRES Track Development Global Scientists

项目摘要

This IRES Track I project will support collaborative research to develop new algorithms and techniques for reliability-aware physical design and optimization of VLSI systems. U.S. students will be trained through collaborative research between two teams -- UCR's VLSI System and Computation Research Lab (VSCLAB) and Tsinghua University's Design Automation Lab. Each year five American students will participate in the IRES program. IRES students will spend 10 weeks (one academic quarter) at UCR and 10 weeks at Tsinghua University, China. Specific IRES collaborative research, education and culture activities are planned to expose U.S. undergraduate or graduate students to the global engineering education and research environment through US-China academic collaboration. The collaborative educational and research activities will provide unique training, mentoring, networking and intellectual development opportunities for students at UCR, which is a growing and Minority Serving Institution. This project thus provides a unique opportunity to contribute to diversity in the U.S. technical workforce. Such international engagement will benefit the students' entire careers and make them more competitive and competent in their careers as scientists and engineers. Furthermore, building long-term connections with top-tier engineering schools like Tsinghua University will help U.S. scientists and engineers maintain competitiveness in the long term. Finally, the joint research will strengthen existing computer engineering research and education programs, and broaden the collaborative research work at UCR. The IRES collaborative project will produce important research advances through joint development of efficient algorithms and design methodologies to address the grand challenges of reliability-aware physical design and optimization of VLSI systems. The researchers will work on the most severe and challenging aspects of verification and design problems of silicon CMOS based integrated systems in current and coming 10nm/7nm nodes: modeling, analysis of long-term interconnect reliability effects such as electromigration (EM), time-dependent dielectric breakdown (TDDB), bias temperature instability (BTI) and reliability-aware physical design and optimization. The mutual interests and complementary knowledge, and established trust between the two research teams is critical for the success of the student training, mentoring and the proposed joint research project. The education and research activities of this joint project consist of following activities: student training, mentoring and intellectual development via pre-trip preparation and on-site visits; new courses and seminar development for proposed research topics; joint research projects and student supervision and publications; promoting and nurturing diverse cohorts of U.S. students; evaluation for continuous improvement of the program.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

IRES Track I 项目将支持合作研究，开发新的算法和技术，用于 VLSI 系统的可靠性感知物理设计和优化。美国学生将通过加州大学河滨分校的超大规模集成电路系统与计算研究实验室（VSCLAB）和清华大学设计自动化实验室这两个团队之间的合作研究接受培训。每年有五名美国学生参加 IRES 项目。 IRES 学生将在 UCR 学习 10 周（一个学季），在中国清华大学学习 10 周。计划开展具体的 IRES 合作研究、教育和文化活动，通过美中学术合作，让美国本科生或研究生接触全球工程教育和研究环境。合作教育和研究活动将为加州大学河滨分校的学生提供独特的培训、指导、网络和智力发展机会，加州大学河滨分校是一所不断发展的少数族裔服务机构。因此，该项目提供了一个独特的机会，为美国技术劳动力的多样性做出贡献。这种国际参与将使学生的整个职业生涯受益，并使他们在科学家和工程师的职业生涯中更具竞争力和能力。此外，与清华大学等顶级工程学院建立长期联系将有助于美国科学家和工程师保持长期竞争力。最后，联合研究将加强现有的计算机工程研究和教育项目，并扩大加州大学河滨分校的合作研究工作。 IRES 合作项目将通过联合开发高效算法和设计方法来取得重要的研究进展，以解决 VLSI 系统的可靠性感知物理设计和优化的巨大挑战。研究人员将致力于解决当前和未来 10nm/7nm 节点中基于硅 CMOS 的集成系统的验证和设计问题中最严峻和最具挑战性的方面：建模、长期互连可靠性影响的分析，例如电迁移 (EM)、时间-相关介电击穿 (TDDB)、偏置温度不稳定性 (BTI) 以及可靠性感知物理设计和优化。两个研究团队之间的共同兴趣、互补知识以及建立的信任对于学生培训、指导和拟议的联合研究项目的成功至关重要。该联合项目的教育和研究活动包括以下活动：通过行前准备和现场访问进行学生培训、指导和智力开发；拟议研究课题的新课程和研讨会开发；联合研究项目以及学生监督和出版物；促进和培养多元化的美国学生群体；该奖项反映了 NSF 的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

期刊论文数量（11）

专著数量（0）

科研奖励数量（0）

会议论文数量（0）

专利数量（0）

Full-Chip Power Density and Thermal Map Characterization for Commercial Microprocessors under Heat Sink Cooling

散热器冷却下商用微处理器的全芯片功率密度和热图表征

DOI：
10.1109/tcad.2021.3088081
发表时间：
2021-01
期刊：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
影响因子：
2.9
作者：
Zhang, Jinwei;Sadiqbatcha, Sheriff;OrDea, Michael;Amrouch, Hussam;Tan, Sheldon X.
通讯作者：
Tan, Sheldon X.

Learning based spatial power characterization and full-chip power estimation for commercial TPUs

基于学习的商用 TPU 空间功率表征和全芯片功率估计

DOI：
发表时间：
2023-01
期刊：
Proc. Asia South Pacific Design Automation Conference (ASP-DAC’23
影响因子：
0
作者：
Lu, J.;Zhang, J.;Jin W.;Sachdeva S.;Tan S.
通讯作者：
Tan S.

Hot-Trim: Thermal and Reliability Management for Commercial Multi-core Processors Considering Workload Dependent Hot Spots

Hot-Trim：考虑工作负载相关热点的商用多核处理器的热和可靠性管理

DOI：
10.1109/tcad.2022.3216552
发表时间：
2023-01
期刊：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
影响因子：
2.9
作者：
Zhang, Jinwei;Sadiqbatcha, Sheriff;Tan, Sheldon X.
通讯作者：
Tan, Sheldon X.

Real-Time Full-Chip Thermal Tracking: A Post-Silicon, Machine Learning Perspective

实时全芯片热跟踪：后硅时代机器学习视角