SBIR Phase I: Integrated Nano-Electro-Mechanical Scanning Probes for Failure Analysis of the 10-Nanometer Node and Beyond

SBIR 第一阶段：用于 10 纳米及以上节点故障分析的集成纳米机电扫描探针

• 批准号: 1448566
• 负责人: Kwame Amponsah
• 金额: $ 15万
• 依托单位: Xallent LLC
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2015
• 资助国家: 美国
• 起止时间: 2015-01-01 至 2015-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1448566&HistoricalAwards=false
• 关键词: SBIR; Phase; Integrated; Nano; Electro

This Small Business Innovation Research Phase I project will focus on the development of a multiple integrated tip scanning probe device for use in semiconductor device failure isolation and analysis. The underlying motivating factor stems from a lack of testing equipment with high resolution and sensitivity necessary for identifying faults as the semiconductor industry shrinks feature sizes to 10 nanometers and beyond. Successful development and use of the integrated device will allow engineers to understand the root cause of failure mechanisms of solid state devices at these advanced nodes. The commercial impact of this new capability for failure analysis on next-generation devices will be profound. The miniaturization of semiconductor devices has led to a decrease in the cost per transistor of seven orders of magnitude in the last 40 years, and new process and measurement technologies are needed to continue this trend. The reduction of transistor size enables high performance devices at a lower cost and lower power. The proposed multiple tip technology will enable the development of these advanced-node highly scaled transistors that will form the platform for the next generation of high-performance electronic devices such as personal computers, cell phones, and healthcare equipment. The intellectual merit of this project is the use of monolithically integrated scanning probes to facilitate the extension of semiconductor failure analysis to devices with feature sizes of ten nanometers or less. Crucially, conventional characterization and test methods are increasingly ineffective when applied to structures smaller than 100 nanometers, causing challenges for engineers in research and development, process control and failure analysis. Subtle defects become increasingly prominent drivers of failure as device size and operating margins decrease, e.g., processing anomalies in thin gate oxides, substrate problems related to doping, and line width variations. These issues can occur at length scales invisible to traditional scanning electron microscopy and optical-based tools, requiring novel approaches. The proposed multiple integrated tip devices leverage powerful nano-electro-mechanical capabilities and scale well even below 10 nanometers. In addition, cost effectiveness of the nanofabrication techniques, combined with monolithic integration of sensing structures and tailoring of the tips would enable robust, high-volume testing, a key need for the semiconductor industry. Research objectives include the fabrication of nanoscale multiple integrated tip devices, atomic force imaging of transistors and active electrical characterization of transistors. The anticipated result is accurate electrical characterization of transistor performance using the multiple integrated tip device.

这个小型企业创新研究阶段I项目将着重于开发用于半导体设备故障隔离和分析的多个集成的尖端扫描探针设备。潜在的激励因素是由于缺乏具有高分辨率和敏感性的测试设备，即作为半导体行业的缩小缩小到10纳米及以后所必需的敏感性。 成功开发和使用集成设备将使工程师能够理解这些高级节点固态设备的故障机制的根本原因。这种新能力对失败分析对下一代设备的商业影响将是深远的。 半导体设备的微型化已导致过去40年来每晶体管成本的七个数量级的成本下降，并且需要新的过程和测量技术来继续这一趋势。 晶体管尺寸的减小可以以较低的成本和较低的功率实现高性能设备。 提出的多个提示技术将使这些高级节点高度缩放的晶体管的开发能够为下一代高性能电子设备（例如个人计算机，手机和医疗保健设备）构成平台。该项目的智力优点是使用单层集成的扫描探针来促进半导体故障分析分析到具有十纳米或更少的特征大小或更少的设备。至关重要的是，当应用于小于100纳米的结构时，常规表征和测试方法越来越无效，从而对研究和开发，过程控制和失败分析的工程师造成了挑战。随着设备尺寸和操作边缘的降低，细微的缺陷成为越来越突出的故障驱动因素，例如，处理薄门氧化物中的异常，与掺杂相关的底物问题以及线宽度变化。这些问题可能会在传统的扫描电子显微镜和基于光学的工具上不可见，需要新颖的方法。拟议的多个集成的尖端设备利用强大的纳米电机机械能力，甚至在10纳米以下甚至低于10纳米。 此外，纳米化技术的成本效率加上传感结构的整体整合和尖端的量身定制，可以实现强大的大量测试，这是半导体行业的关键需求。 研究目标包括制造纳米级的多个集成尖端设备，晶体管的原子力成像以及晶体管的主动电特性。预期的结果是使用多个集成的尖端设备对晶体管性能进行准确的电气表征。