I-Corps: Provable Hardware Design for Integrity and Security
I-Corps:可证明的硬件设计的完整性和安全性
基本信息
- 批准号:1339522
- 负责人:
- 金额:$ 5万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2013
- 资助国家:美国
- 起止时间:2013-05-01 至 2013-10-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Researchers have developed gate-level information flow tracking (GLIFT) technology that allows security analysis to be done on both hardware and software together. The GLIFT technology also allows security properties to be formalized as assertions that are verifiable at design time and allows properties such as non-interference to be proven formally for time-sensitive hardware/software systems. By providing the tools necessary to identify and control undesirable flows of information (such as those that might be injected by an adversary) at the level of hardware, the GLIFT technology captures some of the most insidious and difficult to anticipate security problems. Ultimately this makes it possible to more tightly integrate computing systems from different levels of security in a reliable manner, reducing replication (decreasing size and power), and making system-level evaluation cheaper and faster. Specifically, GLIFT technology provides the capacity of ensuring that a specified subset of inputs could never affect a specified subset of outputs.The GLIFT technology may transform the design of secure and trustworthy computer systems by providing a methodology that allows formal security properties to be tested and verified. It can be used to analyze systems for potential faults and vulnerabilities, as a way to ensure design constraints are understood both software and hardware designers (whom often have no formal security training), and to guide the redesign of those systems to insure such problems no longer exist. It is an enabling technology that allows engineers to efficiently build critical systems, that helps protects users and the general public from damaging events, and ensures that the notion of formal properties are treated a first-order design constraint by the practicing computer system engineers. Researchers believe our technology has the ability create the skills and tools that future embedded hardware and software engineers will need to evaluate the trustworthiness of their systems, and that it will ease the development of those critical systems that we all depend on for our safety and livelihood.
研究人员开发了门级信息流跟踪(Glift)技术,可以一起在硬件和软件上进行安全分析。 Glift技术还允许将安全属性形式化为在设计时可以进行验证的断言,并允许诸如非干预之类的属性被正式证明用于时间敏感的硬件/软件系统。通过提供在硬件级别上识别和控制不良信息流(例如可能由对手注入的工具)所需的工具,Glift技术可以捕捉到一些最阴险且难以预见的安全问题。最终,这使得以可靠的方式从不同级别的安全性中更紧密地集成了计算系统,减少复制(尺寸和功率降低),并使系统级别的评估更便宜,更快。具体而言,Glift技术提供了确保指定的输入子集永远不会影响指定输出子集的能力。Glift技术可以通过提供一种允许对正式安全属性进行测试和测试和可信赖的可信赖计算机系统的设计来改变安全和可信赖的计算机系统的设计。经过验证。它可用于分析潜在的故障和漏洞的系统,以确保对设计限制的理解,既可以理解软件和硬件设计人员(通常没有正式的安全培训),并指导这些系统的重新设计以确保此类问题没有长期存在。这是一项允许工程师有效构建关键系统的能力技术,可以帮助保护用户和公众免受破坏事件的损害,并确保正式属性的概念受到练习计算机系统工程师的一阶设计约束。研究人员认为,我们的技术具有创造技能和工具的能力,即将嵌入的硬件和软件工程师需要评估其系统的可信度,并且可以减轻我们所有人都为了我们的安全和生计而依靠的关键系统的开发。
项目成果
期刊论文数量(0)
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会议论文数量(0)
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Ryan Kastner其他文献
TOP: Towards Open & Predictable Heterogeneous SoCs
顶部:走向开放
- DOI:
- 发表时间:
2024 - 期刊:
- 影响因子:0
- 作者:
Luca Valente;Francesco Restuccia;Davide Rossi;Ryan Kastner;Luca Benini - 通讯作者:
Luca Benini
Gate-Level Information Flow Tracking for Security Lattices
安全网格的门级信息流跟踪
- DOI:
10.1145/2676548 - 发表时间:
2014-11 - 期刊:
- 影响因子:1.4
- 作者:
Baolei Mao;Mohit Tiwari;Timothy Sherwood;Ryan Kastner - 通讯作者:
Ryan Kastner
FKeras: A Sensitivity Analysis Tool for Edge Neural Networks
FKeras:边缘神经网络的敏感性分析工具
- DOI:
- 发表时间:
2024 - 期刊:
- 影响因子:0
- 作者:
Olivia Weng;Andres Meza;Quinlan Bock;B. Hawks;Javier Campos;Nhan Tran;J. Duarte;Ryan Kastner - 通讯作者:
Ryan Kastner
Mangrove Ecosystem Detection using Mixed-Resolution Imagery with a Hybrid-Convolutional Neural Network
使用混合分辨率图像和混合卷积神经网络进行红树林生态系统检测
- DOI:
- 发表时间:
2020 - 期刊:
- 影响因子:0
- 作者:
Dillon Hicks;Ryan Kastner;C. Schurgers;Astrid Hsu;Octavio Aburto - 通讯作者:
Octavio Aburto
Behavioral Synthesis for Hardware Security
硬件安全的行为综合
- DOI:
10.1007/978-3-030-78841-4 - 发表时间:
2022 - 期刊:
- 影响因子:0
- 作者:
Srinivas Katkoori;Omkar Dokur;Rajeev Joshi;Kavya Lakshmi Kalyanam;Md Adnan Zaman;Ariful Islam;Nandeesha Veeranna;Benjamin Carrion Schafer;Rajat Pranesh Santikellur;Subhra Chakraborty;S. Bhunia;Hannah Badier;Jean;Philippe Coussy;Guy Gogniat;C. Pilato;D. Sciuto;Francesco Regazzoni;Siddharth Garg;Ramesh Karri;Anirban Sengupta;Mahendra Rathor;Matthew Lewandowski;Chen Liu;Chengmo Yang;Farhath Zareen;Robert Karam;S. T. C. Konigsmark;Wei Ren;Martin D. F. Wong;Deming Chen;Mike Borowczak;Ranga Vemuri;Steffen Peter;T. Givargis;Wei Hu;Armaiti Ardeshiricham;Lingjuan Wu;Ryan Kastner;Christian Pilato Politecnico;di Milano;Italy Milan;ST Micro;Singapore Singapore;S. Islam - 通讯作者:
S. Islam
Ryan Kastner的其他文献
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{{ truncateString('Ryan Kastner', 18)}}的其他基金
Collaborative Research: SaTC: CORE: Medium: Hardware Security Insights: Analyzing Hardware Designs to Understand and Assess Security Weaknesses and Vulnerabilities
协作研究:SaTC:核心:中:硬件安全见解:分析硬件设计以了解和评估安全弱点和漏洞
- 批准号:
2247755 - 财政年份:2023
- 资助金额:
$ 5万 - 项目类别:
Continuing Grant
Student Travel Support for the International Symposium on Hardware-Oriented Security and Trust (HOST)
面向硬件的安全与信任国际研讨会 (HOST) 的学生旅行支持
- 批准号:
1830895 - 财政年份:2018
- 资助金额:
$ 5万 - 项目类别:
Standard Grant
SaTC: STARSS: Small: Property Driven Hardware Security
SaTC:STARSS:小型:财产驱动的硬件安全
- 批准号:
1718586 - 财政年份:2017
- 资助金额:
$ 5万 - 项目类别:
Standard Grant
TWC: Medium: Collaborative: Computational Blinking - Computer Architecture Techniques for Mitigating Side Channels
TWC:媒介:协作:计算闪烁 - 用于缓解侧通道的计算机体系结构技术
- 批准号:
1563767 - 财政年份:2016
- 资助金额:
$ 5万 - 项目类别:
Continuing Grant
TWC: Small: Employing Information Theoretic Metrics to Quantify and Enhance the Security of Hardware Designs
TWC:小型:采用信息论指标来量化和增强硬件设计的安全性
- 批准号:
1527631 - 财政年份:2015
- 资助金额:
$ 5万 - 项目类别:
Standard Grant
SHF: Medium: Collaborative Research: Building Critical Systems with Verifiable Properties Using Gate Level Analysis
SHF:中:协作研究:使用门级分析构建具有可验证属性的关键系统
- 批准号:
1162177 - 财政年份:2012
- 资助金额:
$ 5万 - 项目类别:
Standard Grant
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