SHF: Medium: Collaborative Research: Building Critical Systems with Verifiable Properties Using Gate Level Analysis
SHF:中:协作研究:使用门级分析构建具有可验证属性的关键系统
基本信息
- 批准号:1162177
- 负责人:
- 金额:$ 40万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2012
- 资助国家:美国
- 起止时间:2012-09-01 至 2015-08-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Computer performance has doubled many times over during the past 40 years, but the very techniques used to achieve these performance gains have made it increasingly difficult to build systems that are provably safe, secure, or reliable. This fact significantly impedes progress in the development of our most safety-critical embedded systems such as those found in medical, avionic, automotive, and military systems. A transformation in the way that these systems are created is needed, one that uses new hardware design techniques, computer architectures, and programming languages to create classes of hardware/software systems with formal and provable safety properties that are verifiable all the way down to the implementation level of bits and logic gates.This research will change the way that hardware and embedded systems designers approach the problem of provable properties, enabling them to directly control and analyze the system at the lowest level and to statically determine if their designs are in compliance with a given policy. For example, if a system must be real-time this property can be verifiable for a full system, from gates to software, by ensuring that the architecture design carefully manages interference through a set of new hardware primitives, software designed to exploit these new primitives, specialized hardware analysis tools, and new design languages. To ensure this technology will have impact beyond academia the PIs are making these new technologies available and accessible through easy to use tools, continuing to include undergraduates at all levels of research to help train a new generation of engineers capable of designing safety-critical systems, and integrating concepts from information assurance into their extensive outreach activities. Over the long term this research will help create the skills and tools that embedded system engineers need to evaluate the trustworthiness of their systems, and it will ease the development of those critical systems on which we all depend on for our safety and livelihood.
在过去的40年中,计算机性能增加了一倍,但是用于实现这些性能增长的技术使得构建可证明安全,安全或可靠的系统变得越来越困难。这一事实极大地阻碍了我们最安全关键的嵌入式系统的发展,例如医疗,航空,汽车和军事系统中发现的系统。 需要创建这些系统的方式的转换,该系统使用新的硬件设计技术,计算机架构和编程语言来创建具有正式和可证明的安全性属性的类别的硬件/软件系统,这些属性一直可验证到一直到该研究将改变硬件和嵌入式系统设计人员处理可证明属性的问题的方式,使他们能够直接控制和分析系统以最低级别的水平,并在静态地确定其设计是否合规,从而改变了硬件和嵌入式系统设计人员的问题的方式具有给定的政策。 例如,如果必须实时实时系统,则可以通过确保架构设计仔细地通过一组新硬件原始图(旨在利用这些新的原始图片)的软件来仔细管理干扰,从而可以对整个系统进行验证。 ,专门的硬件分析工具和新的设计语言。 为了确保这项技术将影响超出学术界的影响,PIS PIS正在使这些新技术可用,并可以通过易于使用的工具进行访问,并继续在各个级别的研究中包括本科生,以帮助培训能够设计安全至关重要系统的新一代工程师,并将信息保证的概念整合到其广泛的外展活动中。 从长远来看,这项研究将有助于创建嵌入式系统工程师需要评估其系统可信度所需的技能和工具,并且它将减轻我们所有人都为了安全和生计而依靠的关键系统的开发。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Ryan Kastner其他文献
TOP: Towards Open & Predictable Heterogeneous SoCs
顶部:走向开放
- DOI:
- 发表时间:
2024 - 期刊:
- 影响因子:0
- 作者:
Luca Valente;Francesco Restuccia;Davide Rossi;Ryan Kastner;Luca Benini - 通讯作者:
Luca Benini
Gate-Level Information Flow Tracking for Security Lattices
安全网格的门级信息流跟踪
- DOI:
10.1145/2676548 - 发表时间:
2014-11 - 期刊:
- 影响因子:1.4
- 作者:
Baolei Mao;Mohit Tiwari;Timothy Sherwood;Ryan Kastner - 通讯作者:
Ryan Kastner
FKeras: A Sensitivity Analysis Tool for Edge Neural Networks
FKeras:边缘神经网络的敏感性分析工具
- DOI:
- 发表时间:
2024 - 期刊:
- 影响因子:0
- 作者:
Olivia Weng;Andres Meza;Quinlan Bock;B. Hawks;Javier Campos;Nhan Tran;J. Duarte;Ryan Kastner - 通讯作者:
Ryan Kastner
Mangrove Ecosystem Detection using Mixed-Resolution Imagery with a Hybrid-Convolutional Neural Network
使用混合分辨率图像和混合卷积神经网络进行红树林生态系统检测
- DOI:
- 发表时间:
2020 - 期刊:
- 影响因子:0
- 作者:
Dillon Hicks;Ryan Kastner;C. Schurgers;Astrid Hsu;Octavio Aburto - 通讯作者:
Octavio Aburto
Behavioral Synthesis for Hardware Security
硬件安全的行为综合
- DOI:
10.1007/978-3-030-78841-4 - 发表时间:
2022 - 期刊:
- 影响因子:0
- 作者:
Srinivas Katkoori;Omkar Dokur;Rajeev Joshi;Kavya Lakshmi Kalyanam;Md Adnan Zaman;Ariful Islam;Nandeesha Veeranna;Benjamin Carrion Schafer;Rajat Pranesh Santikellur;Subhra Chakraborty;S. Bhunia;Hannah Badier;Jean;Philippe Coussy;Guy Gogniat;C. Pilato;D. Sciuto;Francesco Regazzoni;Siddharth Garg;Ramesh Karri;Anirban Sengupta;Mahendra Rathor;Matthew Lewandowski;Chen Liu;Chengmo Yang;Farhath Zareen;Robert Karam;S. T. C. Konigsmark;Wei Ren;Martin D. F. Wong;Deming Chen;Mike Borowczak;Ranga Vemuri;Steffen Peter;T. Givargis;Wei Hu;Armaiti Ardeshiricham;Lingjuan Wu;Ryan Kastner;Christian Pilato Politecnico;di Milano;Italy Milan;ST Micro;Singapore Singapore;S. Islam - 通讯作者:
S. Islam
Ryan Kastner的其他文献
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{{ truncateString('Ryan Kastner', 18)}}的其他基金
Collaborative Research: SaTC: CORE: Medium: Hardware Security Insights: Analyzing Hardware Designs to Understand and Assess Security Weaknesses and Vulnerabilities
协作研究:SaTC:核心:中:硬件安全见解:分析硬件设计以了解和评估安全弱点和漏洞
- 批准号:
2247755 - 财政年份:2023
- 资助金额:
$ 40万 - 项目类别:
Continuing Grant
Student Travel Support for the International Symposium on Hardware-Oriented Security and Trust (HOST)
面向硬件的安全与信任国际研讨会 (HOST) 的学生旅行支持
- 批准号:
1830895 - 财政年份:2018
- 资助金额:
$ 40万 - 项目类别:
Standard Grant
SaTC: STARSS: Small: Property Driven Hardware Security
SaTC:STARSS:小型:财产驱动的硬件安全
- 批准号:
1718586 - 财政年份:2017
- 资助金额:
$ 40万 - 项目类别:
Standard Grant
TWC: Medium: Collaborative: Computational Blinking - Computer Architecture Techniques for Mitigating Side Channels
TWC:媒介:协作:计算闪烁 - 用于缓解侧通道的计算机体系结构技术
- 批准号:
1563767 - 财政年份:2016
- 资助金额:
$ 40万 - 项目类别:
Continuing Grant
TWC: Small: Employing Information Theoretic Metrics to Quantify and Enhance the Security of Hardware Designs
TWC:小型:采用信息论指标来量化和增强硬件设计的安全性
- 批准号:
1527631 - 财政年份:2015
- 资助金额:
$ 40万 - 项目类别:
Standard Grant
I-Corps: Provable Hardware Design for Integrity and Security
I-Corps:可证明的硬件设计的完整性和安全性
- 批准号:
1339522 - 财政年份:2013
- 资助金额:
$ 40万 - 项目类别:
Standard Grant
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