SHF:Small: Benchmarking of Transient and Intermittent Errors and Their Application to Microarchitecture

SHF:Small：瞬态和间歇性错误的基准测试及其在微架构中的应用

• 批准号: 1219186
• 负责人: Murali Annavaram
• 金额: $ 40万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-08-01 至 2016-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1219186&HistoricalAwards=false
• 关键词: SHF; Small; Benchmarking; Transient; Intermittent

Computing infrastructure has been a driving force for our socio-economic progress in the past several decades. From drug discovery to space exploration, every scientific and engineering domain relies on computer systems to accurately analyze complex datasets. Historically, computational accuracy has been taken for granted in all these disciplines, but this notion is changing. While rapidly shrinking transistor dimensions lead to exponential power and performance benefits, the trend is also creating several unwanted side effects in computer system reliability. There are two types of errors that will become prevalent in the near future: (1) multi-bit soft errors where alpha particles and neutrons cause multiple bits to flip at the same time, and (2) intermittent errors that occur due to stress accumulation over the lifetime of a computer. Thus it is critical to benchmark the impact of these errors on the lifetime of a computer chip. Only when the impact is accurately measured is it possible to judiciously deploy solutions to improve reliability. Since any protection scheme comes with a cost, it is necessary to understand when a particular protection scheme being considered, such as parity or single-error-correcting double-error-detecting code, is too much or too little. This project presents two solutions for benchmarking multi-bit soft errors and intermittent errors. This project will develop a unified methodology to benchmark the impacts of single-bit and multi-bit soft errors on caches protected with an arbitrary protection scheme, such as an inter-leaved, block-level or word-level error correcting code. Such a benchmarking framework will significantly enhance a computer designer's ability to objectively evaluate the performance, power, and reliability tradeoffs of various protection schemes proposed for protecting caches. This research also develops a methodology to benchmark the vulnerability of an instruction set architecture (ISA) to intermittent errors. Each instruction in an ISA specification is enhanced to quantify the amount of stress that it is expected to cause on the underlying microarchitecture of a chip. The stress level information from the ISA is combined with operating conditions of the chip to continuously monitor intermittent error probability during application execution. Any unwanted degradation in chip reliability is then tackled by software exception handlers, which trigger redundant execution of vulnerable code. Broader societal impact will result from these research solutions. Benchmarking is essential to objectively evaluate the cost-benefit tradeoffs of various solutions currently being proposed to tackle reliability concerns. Without benchmarking, building a system to meet reliability specifications is a guessing game. By providing the right set of tools to initiate just-in-time error correction and recovery mechanisms, a computer designer can significantly lower the cost of providing reliable computations.

在过去的几十年中，计算基础设施一直是我们社会经济进步的推动力。从药物发现到太空探索，每个科学和工程领域都依赖计算机系统来准确分析复杂的数据集。从历史上看，在所有这些学科中都认为计算精度已被认为是理所当然的，但是这个概念正在改变。尽管快速缩小晶体管尺寸会带来指数的功率和性能优势，但趋势也在计算机系统可靠性中产生了几种不必要的副作用。在不久的将来，有两种类型的误差将变得普遍：（1）多位软误差，其中α颗粒和中子会导致多个位同时翻转，以及（2）由于计算机的寿命中应力积累而导致的间歇性误差。因此，将这些错误对计算机芯片的生命周期的影响进行基准测试至关重要。只有在准确衡量影响的情况下，才有可能明智地部署解决方案以提高可靠性。由于任何保护方案都带有成本，因此有必要了解何时考虑特定的保护方案（例如奇偶校验或单纠正双回交代码）太多或太少。该项目提出了两种解决方案，用于基于多位软错误和间歇性错误。 该项目将开发一种统一的方法，以基于单位和多位软误差对受任意保护方案保护的缓存的影响，例如相互关系，块级或单词级别的错误纠正代码。 这样的基准测试框架将显着增强计算机设计人员客观地评估提出的用于保护缓存的各种保护方案的性能，权力和可靠性权衡的能力。 这项研究还开发了一种方法，以基于指令集体系结构（ISA）对间歇性错误的脆弱性进行基准测试。 ISA规范中的每条指令都得到增强，以量化芯片的基础微体系结构的应力量。来自ISA的应力级信息与芯片的操作条件相结合，以在应用程序执行过程中连续监视间歇性误差概率。 然后，通过软件异常处理程序来解决芯片可靠性中的任何不需要的降解，这会触发弱势代码的冗余执行。这些研究解决方案将造成更广泛的社会影响。基准测试对于客观地评估目前建议解决可靠性问题的各种解决方案的成本效益折衷。如果不进行基准测试，就可以构建满足可靠性规格的系统是一个猜测游戏。通过提供正确的工具来启动即时误差校正和恢复机制，计算机设计人员可以显着降低提供可靠计算的成本。