CSR-PSCE,SM: A Holistic Design Approach to Reliability Using 3D Stacked

CSR-PSCE,SM：使用 3D 堆叠的可靠性整体设计方法

基本信息

批准号：
0834798
负责人：
Murali Annavaram
金额：
$ 40.29万
依托单位：
University of Southern California
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2008
资助国家：
美国
起止时间：
2008-09-01 至 2013-08-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=0834798&HistoricalAwards=false
关键词：
CSR PSCE SM Holistic Design

项目摘要

The future of information technology industry depends on designing computer systems that are tolerant of errors caused by variations in device characteristics. Traditionally system reliability is achieved by replicating critical system components. Since variability induced errors occur slowly over time, replication for the sole purpose of providing reliability is prohibitively expensive for low cost computing platforms. This research explores using 3D stacking to implement redundant components and variability monitoring circuitry on a 3D stacked die. Using 3D stacking the redundant computation blocks can be built using a variation resilient process technology that may be slower than the process technology used for building the primary processor. This research takes a holistic approach to designing the 3D stacked monitoring spanning from innovative microarchitecture solutions to exploiting application's inherent error tolerance. On the microarchitecture front, this research explores the potential for seamlessly reconfiguring the monitoring layer to act in three modes: performance assists, when variability induced errors are rare, or as guard processors, when variability induced errors begin to appear, or as backup processors, when device aging may result in irreparable errors on the primary processing substrate. On the architecture front, this research explores a new exception class called Reliability Aware Exceptions that allow microarchitecture blocks to raise an exception in response to a variability induced error. These software visible exceptions can then be exploited by application classes that are inherently error tolerant and can customized exception handling mechanisms.

信息技术行业的未来取决于设计能够容忍因设备特性变化引起的错误的计算机系统。传统上，系统可靠性是通过复制关键系统组件来实现的。由于可变性引起的错误随着时间的推移缓慢发生，因此对于低成本计算平台来说，仅出于提供可靠性的目的而进行的复制成本过高。本研究探索使用 3D 堆叠在 3D 堆叠芯片上实现冗余组件和可变性监控电路。使用 3D 堆叠，可以使用变化弹性处理技术来构建冗余计算块，该技术可能比用于构建主处理器的处理技术慢。这项研究采用整体方法来设计 3D 堆叠监控，涵盖从创新微架构解决方案到利用应用程序固有的容错能力。在微架构方面，本研究探讨了无缝重新配置监控层以在三种模式下运行的潜力：当可变性引起的错误很少见时，性能辅助，或者当可变性引起的错误开始出现时，作为保护处理器，或者作为备份处理器，当器件老化可能导致主处理基板出现不可修复的错误时。在架构方面，本研究探索了一种称为可靠性感知异常的新异常类，它允许微架构块引发异常以响应可变性引起的错误。然后，这些软件可见的异常可以被本质上具有容错能力并且可以定制异常处理机制的应用程序类利用。