CSR-PSCE,SM: Trade-offs Between Static Power, Performance and Reliability in Future Chip Multiprocessors

CSR-PSCE,SM：未来芯片多处理器静态功耗、性能和可靠性之间的权衡

基本信息

批准号：
0834799
负责人：
Murali Annavaram
金额：
$ 20万
依托单位：
University of Southern California
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2008
资助国家：
美国
起止时间：
2008-09-01 至 2011-08-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=0834799&HistoricalAwards=false
关键词：
CSR PSCE SM Trade offs

项目摘要

As the transistor growth outpaced the design and verification effort in chip design, a large fraction of on-chip transistors are now allocated to storage structures, such as caches. The static power consumed by these storage structures worsen the critical problems of power and thermal issues faced by current chip designs. To reduce the static power, drowsy techniques are used, where inactive components of a storage structure can be placed in a low power state. Unfortunately, drowsy power states increase the susceptibility of transistors to transient errors. Motivated by these problems, this research explores the tradeoffs between static power, performance and reliability in chip multiprocessors. The fundamental contribution of this research is to develop a novel hybrid analytical/simulation framework that allows designers to evaluate the impact of reducing static power on processor reliability and performance. Using this framework this research explores new cache management and cache protocols in chip-multiprocessors and the impact of these new schemes on reliability and performance of a computer system. The framework can also be extended to analyze the power, performance and reliability tradeoffs of other storage structures inside each core such as the reorder buffer, the branch prediction tables, and various instruction and scheduling queues.

由于晶体管的增长速度超过了芯片设计中的设计和验证工作，大部分片上晶体管现在被分配给存储结构，例如缓存。这些存储结构消耗的静态功耗使当前芯片设计面临的功耗和散热问题变得更加严重。为了降低静态功耗，使用了休眠技术，其中可以将存储结构的不活动组件置于低功耗状态。不幸的是，昏昏欲睡的电源状态会增加晶体管对瞬态错误的敏感性。受这些问题的推动，本研究探讨了芯片多处理器的静态功耗、性能和可靠性之间的权衡。这项研究的根本贡献是开发了一种新颖的混合分析/仿真框架，使设计人员能够评估降低静态功耗对处理器可靠性和性能的影响。使用该框架，本研究探索了芯片多处理器中的新缓存管理和缓存协议以及这些新方案对计算机系统的可靠性和性能的影响。该框架还可以扩展为分析每个内核内其他存储结构（例如重排序缓冲区、分支预测表以及各种指令和调度队列）的功耗、性能和可靠性权衡。