SHF: Small: Automated Techniques for Efficient Post-Silicon Validation and Debug of Integrated Circuits

SHF：小型：集成电路高效硅后验证和调试的自动化技术

• 批准号: 1218629
• 负责人: Prabhat Mishra
• 金额: $ 45万
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2012
• 资助国家: 美国
• 起止时间: 2012-07-01 至 2017-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1218629&HistoricalAwards=false
• 关键词: SHF; Small; Automated; Techniques; Efficient

Due to increasing design complexity coupled with shrinking time-to-market constraints, it is not possible to detect all design flaws during pre-silicon validation of System-on-Chip (SoC) designs. Post-silicon validation needs to capture these escaped functional errors as well as electrical faults. Various studies suggest that post-silicon validation consumes almost half of the overall SoC design effort (total cost). A major concern during post-silicon debug is the observability of internal signals since the chip has already been manufactured. Design overhead considerations limit the number of signals that can be traced or stored in a trace buffer. The central objective of this project is to develop automated tools and techniques for efficient post-silicon validation and debug of integrated circuits. To achieve this goal, this project will investigate the synergistic integration of four innovative concepts: i) debug-friendly trace signal selection, ii) efficient trace hardware design, iii) observability-aware directed test generation, and iv) high-level debug to reproduce post-silicon errors. A successful implementation of this research is expected to reduce the post-silicon validation and debug effort by several orders of magnitude.This project will make significant broader impact in several fronts. The tools and techniques resulted from this project will empower designers to reuse pre-silicon verification efforts for post-silicon validation in order to reduce overall validation cost and improve design quality. The outcome of this research has direct impact on everyday life. Improved validation techniques will have double impact: (i) low-cost and high-quality embedded systems (e.g., everyday appliances) for the public and (ii) improved accuracy of the safety-critical devices. Going beyond integrated circuits and systems, some of the analysis and validation techniques resulting from this work can be applied to other areas of science and engineering including validation of embedded software and dynamic monitoring of autonomous systems. This project will integrate research and educational activities through development of courses on post-silicon validation as well as dissemination of research results through publications, seminars, and tutorials. The PI will involve minority undergraduate students in this project through UMMP and SEAGEP programs at University of Florida.

由于设计复杂性的提高加上缩水到市场的限制，因此无法在芯片前芯片（SOC）设计的硅前验证期间检测到所有设计缺陷。后硅验证需要捕获这些逃脱的功能误差以及电故障。各种研究表明，后硅验证几乎消耗了总体SOC设计工作的一半（总成本）。塞利康调试期间的一个主要问题是，由于芯片已经制造，因此内部信号的可观察性。设计开销考虑因素限制了可以追踪或存储在跟踪缓冲区中的信号数量。该项目的核心目的是开发自动化工具和技术，以进行有效的后硅验证和集成电路的调试。为了实现这一目标，该项目将调查四个创新概念的协同整合：i）调试友好的跟踪信号选择，ii）有效的跟踪硬件设计，iii）可观察到的有导性测试生成，iv）高级调试，以重现后核子错误。预计这项研究的成功实施将减少几个数量级的后硅验证和调试工作。该项目将在几个方面产生更大的影响。该项目产生的工具和技术将使设计师能够重复使用后硅后验证的验证工作，以降低整体验证成本并提高设计质量。这项研究的结果对日常生活有直接影响。改进的验证技术将产生双重影响：（i）公众的低成本和高质量嵌入式系统（例如，日常设备），以及（ii）提高安全至关重要设备的准确性。除了集成电路和系统之外，这项工作产生的一些分析和验证技术可以应用于科学和工程的其他领域，包括嵌入式软件的验证以及对自主系统的动态监控。该项目将通过开发有关塞利康后验证的课程以及通过出版物，研讨会和教程对研究结果的传播来整合研究和教育活动。 PI将通过佛罗里达大学的UMMP和SEAGEP计划参与该项目的少数群体本科生。