SHF: Small: Automated Techniques for Efficient Post-Silicon Validation and Debug of Integrated Circuits

SHF:小型:集成电路高效硅后验证和调试的自动化技术

基本信息

  • 批准号:
    1218629
  • 负责人:
  • 金额:
    $ 45万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Continuing Grant
  • 财政年份:
    2012
  • 资助国家:
    美国
  • 起止时间:
    2012-07-01 至 2017-06-30
  • 项目状态:
    已结题

项目摘要

Due to increasing design complexity coupled with shrinking time-to-market constraints, it is not possible to detect all design flaws during pre-silicon validation of System-on-Chip (SoC) designs. Post-silicon validation needs to capture these escaped functional errors as well as electrical faults. Various studies suggest that post-silicon validation consumes almost half of the overall SoC design effort (total cost). A major concern during post-silicon debug is the observability of internal signals since the chip has already been manufactured. Design overhead considerations limit the number of signals that can be traced or stored in a trace buffer. The central objective of this project is to develop automated tools and techniques for efficient post-silicon validation and debug of integrated circuits. To achieve this goal, this project will investigate the synergistic integration of four innovative concepts: i) debug-friendly trace signal selection, ii) efficient trace hardware design, iii) observability-aware directed test generation, and iv) high-level debug to reproduce post-silicon errors. A successful implementation of this research is expected to reduce the post-silicon validation and debug effort by several orders of magnitude.This project will make significant broader impact in several fronts. The tools and techniques resulted from this project will empower designers to reuse pre-silicon verification efforts for post-silicon validation in order to reduce overall validation cost and improve design quality. The outcome of this research has direct impact on everyday life. Improved validation techniques will have double impact: (i) low-cost and high-quality embedded systems (e.g., everyday appliances) for the public and (ii) improved accuracy of the safety-critical devices. Going beyond integrated circuits and systems, some of the analysis and validation techniques resulting from this work can be applied to other areas of science and engineering including validation of embedded software and dynamic monitoring of autonomous systems. This project will integrate research and educational activities through development of courses on post-silicon validation as well as dissemination of research results through publications, seminars, and tutorials. The PI will involve minority undergraduate students in this project through UMMP and SEAGEP programs at University of Florida.

项目成果

期刊论文数量(0)
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会议论文数量(0)
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Prabhat Mishra其他文献

Quantum Measurement Classification Using Statistical Learning
使用统计学习进行量子测量分类
CISELeaks: Information Leakage Assessment of Cryptographic Instruction Set Extension Prototypes
CISELeaks:密码指令集扩展原型的信息泄漏评估
  • DOI:
  • 发表时间:
    2024
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Aruna Jayasena;Richard Bachmann;Prabhat Mishra
  • 通讯作者:
    Prabhat Mishra
Structural and institutional arrangements impacting collective actions in WUAs of West Bengal, India
影响印度西孟加拉邦用水户协会集体行动的结构和制度安排
  • DOI:
    10.1080/07900627.2022.2041407
  • 发表时间:
    2022
  • 期刊:
  • 影响因子:
    3.1
  • 作者:
    Indranil De;Soumyadip Chattopadhyay;Hippu Salk Kristle Nathan;Prabhat Mishra;Akhilesh Parey;S. Dutta
  • 通讯作者:
    S. Dutta
Feedback-Based Steering for Quantum State Preparation
用于量子态制备的基于反馈的转向
Verifying Memory Confidentiality and Integrity of Intel TDX Trusted Execution Environments
验证英特尔 TDX 可信执行环境的内存机密性和完整性

Prabhat Mishra的其他文献

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{{ truncateString('Prabhat Mishra', 18)}}的其他基金

SaTC: CORE: Small: Trustworthy System-On-Chip Design using Secure On-Chip Communication Architecture
SaTC:CORE:小型:使用安全片上通信架构的值得信赖的片上系统设计
  • 批准号:
    1936040
  • 财政年份:
    2019
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
SHF: Small: Design-for-Debug Architecture for Post-Silicon Security Validation
SHF:小型:用于硅后安全验证的调试架构
  • 批准号:
    1908131
  • 财政年份:
    2019
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
CSR: Small: Collaborative Research: Dynamic Reconfiguration for Adaptive Computing in Heterogeneous SoCs
CSR:小型:协作研究:异构 SoC 中自适应计算的动态重新配置
  • 批准号:
    1526687
  • 财政年份:
    2015
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
SaTC: STARSS: Collaborative: IPTrust: A Comprehensive Framework for IP Integrity Validation
SaTC:STARSS:协作:IPTrust:IP 完整性验证的综合框架
  • 批准号:
    1441667
  • 财政年份:
    2014
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
CSR:Small: Novel Techniques for Lossless Data Compression and Efficient Decompression in Heterogeneous Embedded Systems
CSR:Small:异构嵌入式系统中无损数据压缩和高效解压缩的新技术
  • 批准号:
    0915376
  • 财政年份:
    2009
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
CAREER: New Directions in Functional Verification of Heterogeneous Multicore Architectures
职业:异构多核架构功能验证的新方向
  • 批准号:
    0746261
  • 财政年份:
    2008
  • 资助金额:
    $ 45万
  • 项目类别:
    Continuing Grant

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SHF:小型:并发数据结构的模块化自动验证
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  • 财政年份:
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  • 资助金额:
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  • 资助金额:
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