SHF: Small: Design-for-Debug Architecture for Post-Silicon Security Validation

SHF：小型：用于硅后安全验证的调试架构

• 批准号: 1908131
• 负责人: Prabhat Mishra
• 金额: $ 50万
• 依托单位: University of Florida
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2019
• 资助国家: 美国
• 起止时间: 2019-10-01 至 2024-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1908131&HistoricalAwards=false
• 关键词: SHF; Small; Design; Debug; Architecture

System-on-Chip (SoC) is the brain behind computing and communication in a wide variety of systems, starting from simple electronic devices in smart homes to complex navigation systems in airplanes. SoCs are designed today using hardware components, often gathered from untrusted third-party vendors, to meet cost and time-to-market constraints. These hardware components may have vulnerabilities, which an attacker can exploit to leak secret information or cause system malfunction. While researchers have proposed many promising ideas to detect pre-silicon vulnerabilities, the existing solutions are not useful for fabricated chips (referred to as "post-silicon" stage), since it is not possible to observe or analyze all the internal signals. Moreover, it is infeasible to detect a wide variety of vulnerabilities during fabrication and/or validation (at the "pre-silicon" stages) due to runtime and other constraints. Post-silicon security validation will enable secure and trustworthy systems. The impacts of this project are to develop highly secure SoCs through synergistic integration of pre-silicon verification with post-silicon security validation, working closely with industry to enable technology transfer and produce results with practical significance, and training students of diverse backgrounds for the workforce.The primary objective of the proposed project is to develop automated tools and techniques to detect post-silicon security vulnerabilities using an effective combination of simulation-based security validation and side-channel analysis. Specifically, the project will develop a comprehensive list of SoC vulnerabilities, and design a fully automated and cost-effective mechanism for monitoring of runtime security threats. In order to improve the observability in fabricated chips, the project will develop an effective design-for-debug architecture. The project will also utilize side-channel analysis for vulnerability detection. A successful implementation of this project is expected to drastically reduce the overall SoC security validation effort.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

片上系统 (SoC) 是各种系统中计算和通信的大脑，从智能家居中的简单电子设备到飞机上复杂的导航系统。如今，SoC 是使用通常从不受​​信任的第三方供应商收集的硬件组件来设计的，以满足成本和上市时间的限制。这些硬件组件可能存在漏洞，攻击者可利用这些漏洞泄露秘密信息或导致系统故障。 尽管研究人员提出了许多有前途的想法来检测硅前漏洞，但现有的解决方案对于制造芯片（称为“硅后”阶段）没有用处，因为不可能观察或分析所有内部信号。此外，由于运行时间和其他限制，在制造和/或验证期间（在“硅前”阶段）检测各种漏洞是不可行的。硅后安全验证将实现安全且值得信赖的系统。该项目的影响是通过流片前验证与流片后安全验证的协同集成来开发高度安全的SoC，与业界密切合作以实现技术转移并产生具有实际意义的成果，并为劳动力培训不同背景的学生该项目的主要目标是开发自动化工具和技术，利用基于模拟的安全验证和旁道分析的有效组合来检测硅后安全漏洞。 具体来说，该项目将开发一份全面的SoC漏洞列表，并设计一种完全自动化且经济高效的机制来监控运行时安全威胁。为了提高制造芯片的可观察性，该项目将开发一种有效的调试设计架构。该项目还将利用旁道分析进行漏洞检测。该项目的成功实施预计将大大减少整体 SoC 安全验证工作。该奖项反映了 NSF 的法定使命，并通过使用基金会的智力优势和更广泛的影响审查标准进行评估，被认为值得支持。

项目成果

Hardware-Assisted Malware Detection using Explainable Machine Learning

使用可解释的机器学习进行硬件辅助恶意软件检测

• DOI: 10.1109/iccd50377.2020.00113
• 发表时间: 2020
• 期刊: International Conference on Computer Design (ICCD
• 作者: Pan, Zhixin;Sheldon, Jennifer;Mishra, Prabhat
• 通讯作者: Mishra, Prabhat

Dynamic Refinement of Hardware Assertion Checkers

硬件断言检查器的动态细化

• DOI: 10.23919/date56975.2023.10137306
• 发表时间: 2023
• 期刊: Automation & Test in Europe (DATE
• 作者: Witharana, Hasini;Sanjaya, Sahan;Mishra, Prabhat
• 通讯作者: Mishra, Prabhat

Test generation using reinforcement learning for delay-based side-channel analysis

使用强化学习进行基于延迟的侧信道分析的测试生成

• DOI: 10.1145/3400302.3415710
• 发表时间: 2020
• 期刊: International Conference on Computer-Aided Design (ICCAD
• 作者: Pan, Zhixin;Sheldon, Jennifer;Mishra, Prabhat
• 通讯作者: Mishra, Prabhat

Network-on-Chip Trust Validation Using Security Assertions

使用安全断言的片上网络信任验证

• DOI: 10.1007/s41635-022-00129-5
• 发表时间: 2022
• 期刊: Journal of Hardware and Systems Security
• 作者: Jayasena, Aruna;Kumar, Binod;Charles, Subodha;Witharana, Hasini;Mishra, Prabhat
• 通讯作者: Mishra, Prabhat

Towards Secure Classical-Quantum Systems

• DOI: 10.1109/host55118.2023.10133344
• 发表时间: 2023-05
• 期刊: 2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)
• 作者: Daniel Volya;Tao Zhang;Nashmin Alam;M. Tehranipoor;P. Mishra