Reduced Basis Element Methods for Thermal Modeling of Integrated Circuits
集成电路热建模的减少基元方法
基本信息
- 批准号:1217136
- 负责人:
- 金额:$ 15.02万
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2012
- 资助国家:美国
- 起止时间:2012-09-15 至 2016-08-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
The objective of this project is to develop "Reduced Basis Element" techniques for thermal modeling of integrated circuits (ICs). Typical digital IC's are designed using standard cells from "technology libraries", such as NOT, NAND, NOR and XOR gates, flip-flops, adders, multipliers and coders/decoders, etc., each of which may consist of a number of semi-conductor transistors connected by metal interconnects. A normal IC will contain millions of these standard cells and as such it is computationally infeasible to perform detailed thermal simulations of an entire IC. However, the development of accurate and efficient thermal models is becoming increasingly important because of the increasing power density of computing systems. Furthermore, new technologies such as silicon-on-insulator (SOI) and 3D stacking only exacerbate chip-heating problems. The proposed work will capitalize on the geometric repetition inherent in an IC to develop accurate and computationally efficient thermal models. Techniques for dividing and classifying an IC's cells and interconnects into standard geometry blocks will developed. Compact reduced order models for these blocks will then be created and these models will be coupled together to predict the thermal behavior of an entire integrated circuit. The reduced order models will be based on proper orthogonal decomposition analysis of detailed simulation data of individual cells. As such, the reduced order models will not need any ad-hoc modeling assumptions. Coupling procedures will use approaches borrowed from discontinuous Galerkin finite element methods. The proposed approach will enable thermal simulations of an IC with accuracy comparable to that of a direct simulation at a computational cost which is affordable with today's computing machinery. Current computers pack more power into smaller packages than ever before, which often results in significant internal heating problems. Computer chip designers must make compromises based on the temperature distribution in the integrated circuits and need efficient and accurate thermal models to do this. Current models are derived using simplifying assumptions about the heat flows in the integrated circuit and do not provide detailed thermal data. These models limit designers from pursuing more advanced designs. This work aims to develop an efficient, high-fidelity tool that will enable more advanced designs to be tried while maintaining the short design cycle of the semiconductor industry. In addition, the basic framework that will be developed will be applicable to any problem having repeated geometric features such as stacked-cell batteries, solar cell panels, thermoelectric modules, etc. Thus, this technique could enable first-principles-based high-fidelity simulations in a wide range of fields. These simulations will in turn enable the next generation of advanced designs.
该项目的目的是为综合电路(ICS)的热建模开发“减少基础元素”技术。 典型的数字IC是使用来自“技术库”的标准单元设计的,例如Not,NAND,NOR和XOR GATES,触发器,加法器,乘数和编码器/解码器等,每个都可能由金属互连连接的许多半导体晶体管组成。 正常的IC将包含数百万这些标准单元,因此在计算上无法进行整个IC的详细热模拟。 但是,由于计算系统的功率密度不断增长,准确有效的热模型的发展变得越来越重要。 此外,新技术(例如硅启用器(SOI))和3D堆叠仅加剧芯片加热问题。 拟议的工作将利用IC固有的几何重复,以开发准确和计算有效的热模型。 将开发用于将IC的单元和互连分为标准几何块的技术。 然后将创建这些块的紧凑型降低订单模型,并将这些模型耦合在一起,以预测整个集成电路的热行为。 降低的订单模型将基于对单个单元的详细模拟数据的正确正交分解分析。 因此,减少的订单模型将不需要任何临时建模假设。耦合过程将使用从不连续的盖尔金有限元方法借用的方法。 所提出的方法将以准确的速度进行与直接模拟相当的IC进行热模拟,以计算成本,这与当今的计算机可负担得起。 当前的计算机比以往任何时候都更小的包装,这通常会导致重大的内部供暖问题。 计算机芯片设计人员必须根据集成电路中的温度分布进行妥协,并且需要有效,准确的热模型来实现这一目标。 使用有关集成电路中热流的简化假设得出当前模型,并且不提供详细的热数据。 这些型号限制了设计人员追求更先进的设计。 这项工作旨在开发一种高效,高保真的工具,该工具将在保持半导体行业的短时间设计周期时可以尝试更高级的设计。 此外,将开发的基本框架将适用于具有重复的几何特征(例如堆叠电池,太阳能电池板,热电模块等)的任何问题。因此,该技术可以在各个领域启用基于第一原则的高保真模拟。这些仿真反过来又可以实现下一代高级设计。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
专利数量(0)
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Brian Helenbrook其他文献
Brian Helenbrook的其他文献
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