SHF: Small: Collaborative Research: A Novel Method for the Performance Analysis of VLSI Circuits with Severe Parameter Value Variations due to Nano-scale Process

SHF：小型：协作研究：一种用于纳米级工艺导致参数值变化严重的 VLSI 电路性能分析的新方法

• 批准号: 1115564
• 负责人: Sheng-Guo Wang
• 金额: $ 22.5万
• 依托单位: University of North Carolina at Charlotte
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-07-01 至 2015-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1115564&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Novel

The advance of VLSI technology has reached to 32nm feature size and below. For such a nano-scale process, lithography no longer produces the ideal shape/dimension of circuit components in a silicon wafer, and the corresponding electrical parameters may vary as large as 1/3 or more. A major concern in VLSI design is how to evaluate the circuits/systems performance made in such nano-scale process. In the other words, we want to know how much the performance specs will change due to variation in circuit parameters from their nominal values caused by the process uncertainties. The current research on performance robustness analysis is developed mainly along the line of the Monte-Carlo sampling method, or stochastic and statistical analysis methods. They all require a high level of computation complexity to achieve the required accuracy and one would like to avoid the evaluation of large number of samples to validate the performance range of a VLSI circuit/system? In this research the PIs propose a novel method for VLSI circuit performance robustness analysis which does not require evaluation of large numbers of samples. Instead, it computes only a few critical polynomials in frequency domain, or critical systems in time domain. It is a fundamentally new way to analyze VLSI circuit performance robustness. The consequent leap of computation efficiency would make nano-scale VLSI circuit design and its performance robustness analysis practically possible. The objectives of this project are: (i) to develop a solid theoretical basis for the performance robustness analysis of VLSI circuits in both frequency and time domains; (ii) to develop an efficient, novel method for computing VLSI circuit performance variation bounds and distribution (due to the process variation) without using the Monte-Carlo method.The broad impact of this project will be its potentially transformative effect on the robust analysis methods for VLSI circuits. This research will be integrated into the graduate education of the Ph.D. students at the two universities involved, and disseminated by publications in journals and presentations at conferences, a workshop and collaboration with industry, and will hopefully contribute to broad thinking across multiple disciplines.

VLSI技术的进步已达到32nm的功能尺寸及以下。对于这种纳米尺度过程，光刻不再产生硅晶片中电路成分的理想形状/尺寸，相应的电参数可能会变化高达1/3或更多。 VLSI设计的主要关注点是如何评估在这种纳米级过程中所做的电路/系统性能。换句话说，我们想知道，由于电路参数与过程不确定性引起的名义值的变化，性能规格将变化多少。当前对性能鲁棒性分析的研究主要沿着蒙特 - 卡洛采样方法或随机和统计分析方法的线路开发。他们都需要高水平的计算复杂性才能达到所需的准确性，并且希望避免评估大量样品以验证VLSI电路/系统的性能范围吗？在这项研究中，PI提出了一种用于VLSI电路性能鲁棒性分析的新方法，该方法不需要评估大量样品。取而代之的是，它仅计算频域中的几个关键多项式，或时间域中的关键系统。这是分析VLSI电路性能鲁棒性的一种新方法。随之而来的计算效率的飞跃将使纳米级VLSI电路设计及其性能鲁棒性分析几乎可以实现。该项目的目标是：（i）为在频率和时域中对VLSI电路的性能鲁棒性分析建立坚实的理论基础； （ii）开发一种用于计算VLSI电路性能变化界限和分布（由于过程变化）的新方法，而无需使用Monte-Carlo方法。该项目的广泛影响将是其对VLSI电路的强大分析方法的潜在变化效应。这项研究将纳入博士学位的研究生教育中。参与的两所大学的学生，并由会议的期刊和演讲中的出版物传播，这是与行业的研讨会和合作，并希望有助于跨多个学科的广泛思维。