TC: Medium: Collaborative Research: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer Protection

TC：中：协作研究：具有集成多层保护的侧通道防护嵌入式处理器

• 批准号: 0904943
• 负责人: Jia Di
• 金额: $ 10万
• 依托单位: University of Arkansas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-01 至 2011-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0904943&HistoricalAwards=false
• 关键词: TC; Medium; Collaborative; Research; Side

Abstract: Side-Channel-Proof Embedded Processors with Integrated Multi-Layer ProtectionEmbedded digital systems are ubiquitous and may contain sensitive information that could be used for malicious purposes if fallen into the wrong hands. Therefore, strong cryptographic algorithms have been incorporated inside these devices. However, attackers have switched their targets from the cryptographic algorithms themselves to the hardware/software implementations of these algorithms, through ?side-channel? chip measurements. From a hardware perspective, such side-channel attacks can be implemented at both the circuit-level and architecture-level. Although much research has been performed in mitigating side-channel attacks, these solutions are inflexible, unsystematic, and have high overhead. The goal of this research is to develop a universal solution that synergistically combines both architecture-level and circuit-level countermeasures for mitigating all major categories of side-channel attacks, to yield an extremely secure, highly flexible, low overhead digital system design methodology. In this proof-of-concept project, preliminary research will be carried out at both levels. At the architecture-level, novel architectural support to mitigate architecture-level timing and access-driven attacks will be developed. At the circuit-level, Delay-Insensitive Ternary Logic will be utilized to design the new architectural support as well as other key components of a MIPS32 4K-compatible embedded microprocessor. The effectiveness and efficiency of side-channel attack resistance at both architecture-level and circuit-level will be evaluated. Educational modules of circuit-level and architecture-level attack mitigation will be developed. Graduate and undergraduate students, especially from underrepresented groups, will be involved in this project. The research outcome will be disseminated to the academic and industrial communities through journal articles, conference presentations, and appropriate websites.

摘要：具有集成的多层保护式数字系统的侧通道嵌入式处理器无处不在，并且可能包含敏感信息，如果落入错误的手中，可以用于恶意目的。因此，在这些设备中已纳入了强大的加密算法。但是，攻击者已通过“侧渠道”将其目标从加密算法本身转换为这些算法的硬件/软件实现？芯片测量。从硬件的角度来看，可以在电路级和体系结构级别上实现此类侧通道攻击。尽管在减轻侧道攻击方面已经进行了大量研究，但这些解决方案是不灵活的，非系统性的，而且开销很高。这项研究的目的是开发一种通用解决方案，该解决方案协同结合体系结构级别和电路级的对策，以减轻侧通道攻击的所有主要类别，以产生一种极为安全，高度灵活的，低架空的数字系统设计方法。在这个概念验证项目中，将在两个级别进行初步研究。在体系结构级别，将开发用于减轻建筑级的时机和访问驱动式攻击的新型建筑支持。在电路级别，将利用对延迟不敏感的三元逻辑来设计新的体系结构支持以及MIPS32 4K兼容的嵌入式微处理器的其他关键组件。将评估体系结构级别和电路级别的侧通道攻击性的有效性和效率。将开发出电路级和建筑级别攻击缓解的教育模块。该项目将参与研究生和本科生，特别是来自代表性不足的小组的学生。研究结果将通过期刊文章，会议演讲和适当的网站传播到学术和工业社区。