EHCS: Dynamic Vertically Integrated Power-Performance-Reliability Modulation in Embedded Digital Signal Processors

EHCS：嵌入式数字信号处理器中的动态垂直集成功率性能可靠性调制

• 批准号: 0834484
• 负责人: Abhijit Chatterjee
• 金额: $ 22万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2008
• 资助国家: 美国
• 起止时间: 2008-09-15 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0834484&HistoricalAwards=false
• 关键词: EHCS; Dynamic; Vertically; Integrated; Power

Serious new technical challenges are barriers to advances in microelectronics technology as technology scaling comes up against fundamental limits of material properties and lithography. Large process variations and other random performance and power constraining imperfections are now being observed as microelectronic devices are scaled down to atomic dimensions. This requires that module level performance in electronic designs be pessimistically guardbanded to ensure proper overall system level functionality, forcing systems to operate at performance levels far below the inherent capability of the underlying design fabric. In addition, embedded DSP systems must be designed to work under worst case operating conditions resulting from ill-conditioned input signals. Wider guardbands from increasing performance and input signal variability in future technologies can negate most of the performance benefits of scaling, stalling a key payoff from Moore?s Law for embedded systems. In such an environment, introduction of new scaled devices will be cost-effective only if the guardbands can be controlled down to acceptable margins, despite the presence of these uncertainties. This remains a major unsolved challenge, especially for embedded DSP processors that must be concurrently optimized for system level power, performance and reliability. To address these problems, this project is developing the concept of test, diagnosis and continuous signal monitoring enabled dynamic circuit-architecture-algorithm co-modulation (or co-tuning) for both static (procees) and dynamic (input signal) uncertainties. Under this new design paradigm, feedback driven reconfiguration control mechanisms involving circuitry and software (?tuning knobs?) are designed into the IC to support power-performance trade-off and reliability recovery post manufacture. The research pursues vertically integrated circuit-architecture-algorithm tuning methods that offer 10X benefits over optimizations performed at a single level of the design hierarchy. The diagnostic information generated is used to dynamically optimize (post-manufacture) individual module level behavior to optimize system level performance, power and reliability metrics via specially designed hardware and software control mechanisms. In this way, each instantiation of a design adapts to the maximum performance, power, and reliability levels it is capable of in the presence of process variations and adverse operating conditions. Graduate students working on the project receive a unique kind of training in this multidisciplinary research, which together the fields of digital design and test, control systems, embedded digital signal processing architectures, and algorithms. The students participate in summer internship programs with industry. Through joint efforts at Georgia Tech, Auburn University, and Tuskegee University, this project also actively supports the goals of recruiting more U.S. citizens, women and minorities to graduate programs.

由于技术扩展遇到了材料特性和光刻的基本限制，严重的新技术挑战成为微电子技术进步的障碍。随着微电子器件缩小到原子尺寸，现在可以观察到大的工艺变化以及其他随机性能和功率限制缺陷。 这要求对电子设计中的模块级性能进行悲观保护带，以确保正确的整体系统级功能，迫使系统以远低于底层设计结构固有能力的性能水平运行。 此外，嵌入式 DSP 系统必须设计为能够在由病态输入信号导致的最坏情况操作条件下工作。未来技术中提高性能和输入信号可变性带来的更宽的保护带可能会抵消扩展带来的大部分性能优势，从而阻碍嵌入式系统摩尔定律的关键回报。在这样的环境中，尽管存在这些不确定性，但只有当保护带能够控制在可接受的范围内时，引入新的扩展设备才具有成本效益。这仍然是一个尚未解决的重大挑战，特别是对于必须同时针对系统级功耗、性能和可靠性进行优化的嵌入式 DSP 处理器。为了解决这些问题，该项目正在开发测试、诊断和连续信号监控的概念，从而实现静态（过程）和动态（输入信号）不确定性的动态电路架构算法协同调制（或协同调谐）。在这种新的设计范例下，涉及电路和软件（“调谐旋钮”）的反馈驱动重配置控制机制被设计到 IC 中，以支持功率性能权衡和制造后的可靠性恢复。该研究追求垂直集成电路架构算法调整方法，与在设计层次结构的单一级别执行优化相比，该方法具有 10 倍的优势。生成的诊断信息用于动态优化（制造后）各个模块级行为，通过专门设计的硬件和软件控制机制来优化系统级性能、功耗和可靠性指标。通过这种方式，设计的每个实例都可以适应在存在工艺变化和不利操作条件的情况下能够达到的最大性能、功率和可靠性水平。从事该项目的研究生在这项多学科研究中接受了独特的培训，这些研究涵盖了数字设计和测试、控制系统、嵌入式数字信号处理架构和算法等领域。学生参加行业暑期实习计划。通过佐治亚理工学院、奥本大学和塔斯基吉大学的共同努力，该项目还积极支持招募更多美国公民、女性和少数族裔参加研究生课程的目标。